Needed some info on output capacitor for LDO .Based on stability requirements ,one can have the output cap from 1uF to 3uF based on the dominant pole location & scale the ESR accordigly so as to have the loop stability .My question is how to choose the value of the cap ? What is the ratio between Ropass and Resr ?
I would rather know that current drain by the load. If the load is pulse load (a switching source), the capacitor value should be different. For the tantalum cap or ceramic cap, because of the low ESR in nature, the case of the unstability will be minimum.
Load is pulse load .Ropass is fixed by Vdssat of PMOS & max load current .
The non dominant pole due to pass transistor gate capacitance is at the UGB .
Let's say its at 1Mhz frequency .
Pdominant =1/Ropass*Cout
My question are
Can I pick any frequency for dominant pole location and calculate Cout ,later scale Resr for stability .I think Tantalum cap >1uF have stable ESR .I think I can select a lower cap(around 1uF) and still achive stability instead of selecting Big cap like 2 to 3uF .
Second thing I would like to know is is it mandatory to ensure that pole due bypass cap falls with in UGB in open loop analysis.
Dear Mady,
LDO is a 3 pole and one zero system. I hope we agree on that.
So system is inherentally unstable.
Now assume we have somehow cancelled the non-dominat pole and the zero, if we have our bypass pole inside UGB the pase margin and stability are hit.
I would ensure in my design that the bypass pole is way beyond the UGB