A race condition is a result of poor design for a latch or flip-flop. It denotes a condition in which the data and clock are changing at the same time and the result depends on which one wins.
In rare cases the data can be exactly on the threshold between a 0 and 1 and when the clock changes, the output actually stays between a 0 and 1 for a while (for example in a 5V system the output may stay around 2.5 volts for a short time (microseconds, maybe). When this happens the output is said to be 'metastable'. This could have serious effects on the operation of the system and worse, could be virtually impossible to duplicate and thus very hard to find and fix.
This same problem can exist at inputs to a logic gate and produce unwanted 'glitches'.
In order to prevent these design flaws, the designer needs to do a 'worst case timing analysis' on all the logic. This analysis uses propagation delays, rise and fall times, threshold points, etc. to calculate timings. He must do both minimum and maximum times for each device and choose the worst case combinations. In a large system this can be very time consuming but there are tools to aid in this analysis.
Power gating is used to simply turn the clock on and off (or gate the clock) to sections of logic that aren't in use for periods of time. This results in a reduction in power.