CTS
Hi
In the current chips we are synthesizing millions of gates at the frequencies of GHz. More over while synthesizing we are synthesizing the synchonous logic which is very sensitive of clk for more no stages including hundreds/thounds of gates with a single clk signal.. All these tasks are cleary recognizable if and only if their unique dependednt signal (clk signal) reaches all the gates at the required point of time.. A slighest difference like a nano second will make a very huge impact on the functionality of the chip (especially at the high frequencies exceeding 100MHz.) and chip can be safely thrown into the dustbin.. So to avoid that we need to ensure that the most dependednt/reference signal of the chip (clk) is proprely routed.. ensure that it reaches every part and corner of the chip at same time/required time.. This cannot be done at the time of ordinary routing as the algorithm cannot efficiently handle the clk signal and normal signal in the same way..
case 1: It will either treat clk signal as normal signal and route it or
case 2: every other signal as clk signal and produce signal trees just as clk trees
this will depend on the type of algorithm people use for routing.. Both the cases are dangerous as case 1 results greater skew between two different clk points and result in functionality failure of the chip and case 2 result in producing h-trees/x-trees for each and every signal resulting in over utilization of metal resources and resuting in high congestion/power losses/ heat generation etc.,
So we need the clk to be handled seperately.. That is why CTS (Clock Tree Synthesis) is there..
regarding what is done at CTS..
As I had already explained you that the clk signal need to reach the each and every part and corner of the chip at the same time.. Given the frequency of the clk as constant, how to acheive this task of reaching a signal at the same point of time to the nearest and farthest point..
the answer is to route in such way that the distance from the clk source pin to the nearest and farthest point in the chip is same.. that means more swrils/rouond about routing for nearest point and straight line routing for farthest pin.. simple naa..
No. It looks simple.. but imagine doing in this way and syncronizing millilons of such points across the chip..It is a near impossible task, even if it is acheivable, it takes a near life time to do that.. So the solution is.. divide the chip into different part so as the clk signals.. so there will be lots of internally generated clks each covering a small portion of the chip (known as clk domains...) so the tool ensures that every point in these clk domains are reached at the same time. so the whole chip is divided into larger and lesser no.of blocks.. consider each block as a point (as each point in the block can be reached at same time.) so the no.of points reduced.. now play the same old game of round about routing path for nearest point(block) and nearest path for farthest point(block) handling the actual clk signal across different clk domains..
This is what is done when CTS is running.. Now I guess you can understand this and infer answers for the remaining of your questions..
Anyway breif anwers are in CTS spec file what points should be mapped at the same point of time will be specified along with their contraints.. In optimisation.. It will refine the work it had done for better timing..
Hope you understnd my long explanation.. If any thing mentioned wrong anyone can correct me..