what is the problem with the FDCE

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Serwan Bamerni

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Hello everyone

Dear all Xilinx users

when i investigate the synthesis report of my project
i saw the following values

FlipFlops/Latches : 71
# FDC : 1
# FDCE : 50
# FDE : 20

in which I have a large number of FDCE and FDE, although I didnt infare such number of flip flop.
how this large number of flip flop is infared

below is my code and it can be seen that i never use such number of flip flop

also how one can decrease the number of FDCE and FDE

 

below is my code and it can be seen that i never use such number of flip flop
I see quite a lot of FFs generated by your code. There are FFs for
1. Each signal bit that's assigned under control of rising_edge(clk)
2. Each variable bit that has to be kept between clock cycles like odd_o1, odd_o2, odd_o3, even_o1
 
You have a lot of FDCE and FDE flipflops because you have enables in your code.
Code:
--anything using a templete like this:
Process(clk)
  If rising_edge(clk) then
    If some_signal = '0' then
      ...
    end if;
  end if;
End process;
 
I see quite a lot of FFs generated by your code. There are FFs for
1. Each signal bit that's assigned under control of rising_edge(clk)
2. Each variable bit that has to be kept between clock cycles like odd_o1, odd_o2, odd_o3, even_o1

thank you for your reply
you mean that variable also infer flip flop

- - - Updated - - -


thank you for your reply
I previously think that only signals infer registers
 

Variables can infer registers (=act as storage elements) depending on their usage.

If a variable is read during the sequential process before it is written, it must preserve the value from the previous clock cycle and thus infer a register. In addition, some variables are written conditionally in your code.
 

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