What is the performance of NIOS kit from Altera?

[davorin]

nios performance

Can someone recommend the NIOS kit from Altera to use as platform for replacing an embedded coldfire system?

- What is the expected performance running with SDRAM?
- Anybody tried to integrate ethernet MAC softcore in it?
- Or is it better to use PowerPC CPU instead for better price/performance?
- How to configure FPGA after booting? Special CPLD for reading configuration from flash?

So far I got the impression that softcores on FPGA are just a nice toy to play with and really a competition to normal RISC CPU's since FPAG performance is rather slow (like LEON, OR1K) like 20 - 50MHz and only makes sense when going ASIC (300MHz with OR1K).

 

[radix]

nios ethernet performance

I am using the Nios developement board with a Stratix FPGA. The board clock is fixed at 50 Mhz and the bus width to the SDRAM and MAC is 32-bits. I haven't done any benchmarking but be aware that the SDRAM and MAC share the address and data bus.

I'm not using the Nios processor but am using the Stratix to communicate with the MAC directly. Accessing the MAC using the async interface (which is how the Nios does it) means you can access a 32-bit word every 100 ns which translates to 320 Mbps. Since you have to use the same bus for rx/tx the max theoretical throughput is about 160 Mbps. The actual throughput is going to be less since you have to read and write some MAC registers whenever you switch between rx/tx mode. However, it should be close to 100 Mbps. If you plan on using the SDRAM for packet buffering however, you're not going to get anywhere close to the 100 Mbps throughput.

The Nios development board also allows you to add to additional MAC daughtercards. Be advised that the daughtercards only allow 16-bit accesses to the MACs on board.

Radix