What is the output of 2 input AND gate with '0' and a meta-stable value?

[sps0987]

In physical devices, what is the output of the AND gate when one input is '0' and the other is a meta-stable value? Is the output 0, since one input is '0', therefore the other input is a don't care? Or could the output be meta-stable as well?

 

[stenzer]

Hi,

have a look at the AND gate truth table. As you should see, as long as ONE of the pins is zero (LOW), the output is also zero (LOW), regardless which state is present at the other input.

BR

 

[sps0987]

Hi,

have a look at the AND gate truth table. As you should see, as long as ONE of the pins is zero (LOW), the output is also zero (LOW), regardless which state is present at the other input.

BR

Yea, I just wonder if the physical implementation had really taken the metastability issue into consideration.

 

[crutschow]

Yea, I just wonder if the physical implementation had really taken the metastability issue into consideration.

What physical implementation?
What issue?
Metastability is just the signal being in an unknown state.
Since the AND gate, with one input low, doesn't care what the other input state is, how can metastability be an issue for the AND gate output?

 

[sps0987]

What physical implementation?
What issue?
Metastability is just the signal being in an unknown state.
Since the AND gate, with one input low, doesn't care what the other input state is, how can metastability be an issue for the AND gate output?

That's what I'm trying to understand. I'm guessing for an AND gate, if one input is 0, then the output regardless of the other input will be 0. But if one input is 1, and the other is metastable, then the output is metastable as well?

 

[crutschow]

But if one input is 1, and the other is metastable, then the output is metastable as well?

Seeing as how the output of the AND gate will follow the metastable input when then other input is high, then yes the output will look like the metastable input.
That's just the way any AND gate works.
It has nothing directly to do with the "physical implementation" or any other issue.

If you are concerned about metastability, then you need to eliminate that as a problem in the circuit.

 

[std_match]

Metastability is different from what we normally mean with "unknown" for a digital signal ('X' in simulation).
It is when the output from a flip-flop/register settles later than normal due to a setup/hold violation.
The flip-flop/register becomes "analog" during the extended settling time, with possible signal levels somewhere in-between '0' and '1'.

If you feed an unknown but not metastable signal to both inputs of a 2-input XOR gate, the output is '0' (in the real world, maybe not with an 'X' input signal in simulation).
If you do the same with a metastable input signal, the output is unknown because one input may see it as '0' and the other may see it as '1'. The output can be '0', '1', can have glitches or be in-between like the metastable input.

If you have '1' to one input of an AND gate, and the other input is metastable, the output is truly "unknown".

 

[KlausST]

Hi,

metastability is a problem of FlipFlops, thus not related logic gates.
Metastability causes the output of a FF to get an invalid level between clear LOW and clear HIGH.

Now let´s re phrase the initial question:

What is the output of 2 input AND gate with '0' and an invalid input level?​

With all AND circuit´s I´ve seen (TTL, CMOS) they all work the same:
The output is 0 when one input is 0 independent of the other´s input (0, 1, else)
The 0 is dominant.

Klaus

 

[FvM]

Output glitches of logic circuits with changing inputs can be an issue. They are known e.g. for FPGA LUT with multiple inputs changing simulataneously and they may also occur for an XOR gate under certain condidtions. In case of the discussed basic NAND gate, the problem can hardly occur, even if you assume large delay variations between the transistors forming the gate.

 

[std_match]

Glitches are normally time-limited. A metastable condition from a flip-flop/register can theoretically go on forever, but the probability decreases rapidly with time.

The metastability MTBF increases rapidly when the number of synchronizer stages increase.
2 stages are common, but 3 or more stages can be needed to get an acceptable MTBF.