what is the need for post cts opt stage after cts apart from targeting hold violations in VLSI?

[Girija_123]

Will you please let me know what is the need for post cts opt stage after cts apart from targeting hold violations in VLSI?

 

[ThisIsNotSam]

Post CTS stage means the clock is routed, but the rest of the still is not routed. At this point you can estimate clock insertion delay and clock arrival times with good precision, so it is a good idea to go back to your optimization and see if timing is still met. In fact, modern CTS runs opt internally as a default option, it is hard to force the tools NOT to optimize during CTS.

After CTS, comes routing. After routing, precise wire lengths will be known and extraction can be run. Then timing can be calculated and the circuit can be optimized accordingly. So you need another round of opt. This is rather straightforward, but maybe I don't get your question. I don't see how hold is relevant here. Setup is the primary target of opt.

 

[Girija_123]

In the latest PnR automation flows, hold fixing will be enabled as soon as clock routing is done. Thank you very much Sam, your first part of the reply explains clearly the need for post cts optimization stage.

 

[ThisIsNotSam]

In the latest PnR automation flows, hold fixing will be enabled as soon as clock routing is done. Thank you very much Sam, your first part of the reply explains clearly the need for post cts optimization stage.

It might be enabled to ease timing closure in the post route stage.
but this trick is relatively old. I have had designs where we enabled hold fixing after placement already. I would say this is an extreme case, however.

 

[diaz080]

might be looking for answer related to clk gate enable paths.