What is the need for doing static timing analysis(STA) in ASIC design flow?

[sivarajesh]

can anybody explain what is the need for doing static timing analysis(STA) at beofre floorplanning and after floor planning in the ASIC design flow?

 

[au_sun]

ASIC STA

We have to do STA before and after floorplanning for Checking any timing violation.

When u do prelayout STA, u have to check for any timing violation in the Synthesis Netlist. this is to check the quality of the Synthesis netlist.

When u do STA after floorplanning, we have to ensure that the floorplanning doesnt change any timing of the netlist.

 

[joe2moon]

Re: ASIC STA

Before floorplan,
1) check if the timing constraints are reasonable, and
2) check the quality of netlist with estimated wire-load.
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After floorplan,
--> check the quality of floorplan (the timing of placed netlist with net parasitics.)
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[dsairajkiran]

Re: ASIC STA

there may be problem with the netlist itself,so zero RC check is must before floorplanning

 

[dsairajkiran]

Re: ASIC STA

this pdf may be useful

 

[cnspy]

ASIC STA

sorry, I do not find the pdf

 

[ankit12345]

ASIC STA

What tool ur using???
If its PT....the they have explained clearly in user guide.

for PT user guide......search in edaboard.

 

[amitk3553]

Re: ASIC STA

We have to do STA before and after floorplanning for Checking any timing violation.

When u do prelayout STA, u have to check for any timing violation in the Synthesis Netlist. this is to check the quality of the Synthesis netlist.

When u do STA after floorplanning, we have to ensure that the floorplanning doesnt change any timing of the netlist.

What are the critical points in prelayout STA??? or challenges???