[SOLVED] What is the necessity of having a low impedence path in logical circuits

[iVenky]

I am currently reading "Digital Integrated Circuits" by Jan Rabaey. I have some doubts regarding the necessity of having a path from the output to the supply or ground

Here's what he says-

"CPL belongs to the class of static gates, because the output-defining nodes are always connected to either Vdd or GND through a low-resistance path. This is advantageous for the noise resilience."

What does this has to do with noise resilience?
He is very specific about having a path from the output to the supply or ground. What's the problem if we leave the output node floating?

Once again he says somewhere-

"When designing static-pass-transistor networks, it is essential to adhere to the low-impedance rule under all circumstances."

Could you please clear me these doubts?

Thanks in advance.

 

[FvM]

I would insist on the requirement, that a net representing logic states by voltage levels must not be floating. It can have a low impedance termination at the sender, at the receiver, or possibly at both sides. For low power operation, only source side termination comes in to consideration.

 

[iVenky]

I would insist on the requirement, that a net representing logic states by voltage levels must not be floating. It can have a low impedance termination at the sender, at the receiver, or possibly at both sides. For low power operation, only source side termination comes in to consideration.

What will happen if it is floating? What's wrong in there?

Thanks in advance.

 

[FvM]

A floating node has an undefined state. A high impedance node will change it's state already with very small current's injected to it, e.g. by near by switching nodes with a coupling capacitance.

Aren't these trivial facts?

 

[iVenky]

Aren't these trivial facts?

Sorry to disappoint you. I didn't realize it until now.

Thanks.