[SOLVED] What is the maximum size about spartan3 FIFO?

Hi
I have spartan3 fpga.

When i have make fifo by coregen, i'll just can make under 2048 size.
But i need more size. So what is the maximum size of spartan3 FiFo?
And What am i do ?

it depends on WHICH device you are using-they have different memory amounts, you know. When you go run coregen it will tell you how much memory it needs to implement your FIFO. If you can't fit it in your existing device you'll have to use a bigger one.

+1 what Barry said, also, you haven't told us how many bits wide your FIFO is, and of course that also figures into how much memory / gates you need. Spartan 3A series goes from 50k gates & 54kb RAM up to 1400k & 576kb of RAM, so it is easy to stay in the family and migrate the design to the larger parts.

You my want to check the data sheet https://www.xilinx.com/support/documentation/data_sheets/ds099.pdf. Check page 29.

As ftsolutions says, it depends of the width, and also on specifically which FPGA are you using. Some have more BRAM than others. Also consider that you also could use Distributed RAM( Try not to use this one. Verify the synthesis report if it is a BRAM or distributed. the last one would take much longer to synthetize than BRAM).

Also consider that if you use a BRAM, try to use the sizes that are in page 29(in case you want to maximize the usage). Otherwise, you could end up "wasting" some memory because. I could explain more if you need too.

Could you please let me know more ?

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Could you please let me know more ?

Nicolás Celedón said:

You my want to check the data sheet https://www.xilinx.com/support/documentation/data_sheets/ds099.pdf. Check page 29.

As ftsolutions says, it depends of the width, and also on specifically which FPGA are you using. Some have more BRAM than others. Also consider that you also could use Distributed RAM( Try not to use this one. Verify the synthesis report if it is a BRAM or distributed. the last one would take much longer to synthetize than BRAM).

Also consider that if you use a BRAM, try to use the sizes that are in page 29(in case you want to maximize the usage). Otherwise, you could end up "wasting" some memory because. I could explain more if you need too.

Click to expand...

u24c02 said:

Could you please let me know more ?

Click to expand...

Could you be more specific? What part of the datasheet (which you of course have read by now) was unclear?

To solve this faster. At least review the datasheet, everything about BRAM. Then you should specify wich FPGA are you using (model and number of gates, appears on top of the chip), and finally the width of the data that you want to put in the fifo and an estimate number of data values.

If you are not sure of the width nor the number of data values, you should explain a little the application that your trying to achive. Otherwise, imposible to help

Nicolás Celedón 's answers.

mrflibble said:

Could you be more specific? What part of the datasheet (which you of course have read by now) was unclear?

Click to expand...

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Nicolás Celedón said:

To solve this faster. At least review the datasheet, everything about BRAM. Then you should specify wich FPGA are you using (model and number of gates, appears on top of the chip), and finally the width of the data that you want to put in the fifo and an estimate number of data values.

If you are not sure of the width nor the number of data values, you should explain a little the application that your trying to achive. Otherwise, imposible to help

Click to expand...

Actually, i have already know about the width what is 8.
But when i have add more options in generation process FIFO, i can't use almost size.
But when i have at least options in generation process FIFO, i cant use almost size.

So This part is my question's point.

A 2048x8 FIFO requires 16,384 bits. Even the smallest Spartan has over 50K bits. So you must be doing something wrong, or else you've used up the memory elsewhere.

can you tell me what is the size of your file??..how many bits does it have...usually a single port bram has 18000 bits(18Kb) so that means that you can use 2250x8 data values....2250 is the length of your fifo and 8 is the width of the data in each address position of fifo i.e 2250 locations.

sreevenkjan said:

can you tell me what is the size of your file??..how many bits does it have...usually a single port bram has 18000 bits(18Kb) so that means that you can use 2250x8 data values....2250 is the length of your fifo and 8 is the width of the data in each address position of fifo i.e 2250 locations.

Click to expand...

No you cant. If you read the documentation, you'll see max size for 8 bit is 2048 (the same for 9 bit also). BRAMs are designs to be 8 bits + parity bit. You can use the parity bit as an extra data bit, but if you do not, you lose the extra space. How would a BRAM with 2250 location work?

i was not aware of this parity bit but however bram initializes itself the number of bram required based on the depth and data given...however the mentioned .coe file should have right syntax and depth,radix values.

sreevenkjan said:

can you tell me what is the size of your file??

Click to expand...

Why are you asking about a file? The OP is trying to implement a FIFO.

u24c02 you still haven't told us the FIFO depth. you've given us 8-bits as the width, but what is the depth you are trying to achieve?

regards

ads-ee said:

Why are you asking about a file? The OP is trying to implement a FIFO.

u24c02 you still haven't told us the FIFO depth. you've given us 8-bits as the width, but what is the depth you are trying to achieve?

regards

Click to expand...

OP said 2048 in initial post

barry, he said he could only make a 2048 but wanted something bigger. My question is what is his required depth.

u24c02, you problem is that you can't create the FIFO or the problems appears during synthesis or mapping?. Right now I just put a fifo of 4096x8, and had no problem with BRAM. I didn't create a whole project but it creates the module. The only thing is that in this case it will use 2 BRAM, and if you want a deeper FIFO, it will use more BRAM blocks.

If for some other reason, it still doesn't work you could always put to fifos in series, or doing the verilog your self. In this last case it would take more effort, controlling the number of items in the memory and the addresses ( It helps using the basic examples of BRAM declaration shown in the menu Edit->Language Templates >>> Verilog->Synthesis Construct->Coding examples->RAM->Block Ram-> and choose sinle port or dual port, whatever fits to your needs).

If this doesn't help, you need to provide more info of your project, with some many variables it's hard to focus on the specific solution to your problem.

Also, you could also review the datasheet of the fifo's. It might be usefull to understand the way they work.