what is the max transition and max capacitance

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mazouzi

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hi

can any one tell me what's are max transition and max capacitance and how we can juge if they are good or not !!!

thanks
 

The library timing defined the timing table with two axes: the output capacitance and the input transition, and also indicates max trans/cap for each pins, this value could be the limit of the axes, or smaller (not really good if this is higher than the axes).
The max capacitance and max transition violations only indicate that the max trans/cap of the pins is repected, to mentionne to the designer, the timing extracted from the table has been extrapolated, and could not correspond to the reality.
if you are the difference is important relative to the axes limit, the correspondant timing calculation must have a huge probability to be wrong, and so the hold/setup reported be corrupted.
So before looking to the setup/hold time report, you must have the trans/cap violations clean or so small than the impact is reduce.
Or in other formulat, you report the setup/hold time for all paths which have a trans/cap violations and if the setup/hold time margin is important ignore the max/trans report.
 

thnks rca for responding i m new in backend please

what do yo mean by axes !! and where i can find the librairy timing !! :-(
and how we can corect the max tran/cap violation if they exist !!


thnks
 

rca said:
So before looking to the setup/hold time report, you must have the trans/cap violations clean or so small than the impact is reduce.
Click to expand...

So rca - Lets consider PT - so all you are saying is first of all check for Max trans/cap, fix it, and then you check setup/hold and fix it?? Am I interpreting it correctly?

Now if we go back to DC - Is the same holds true? I know that we'll not fix hold in DC (provided it is not huge)
Can you please tell?

Along with that
rca said:
Or in other formulat, you report the setup/hold time for all paths which have a trans/cap violations and if the setup/hold time margin is important ignore the max/trans report.
Click to expand...
It has to be - you report the setup/hold time for all paths which "don't" have a trans/cap violation....
Can to enlarge it? Thanks..
 

mazouzi said:
thnks rca for responding i m new in backend please
what do yo mean by axes !! and where i can find the librairy timing !! :-(
and how we can corect the max tran/cap violation if they exist !!
thnks
Click to expand...
Open a .lib (liberty) file, and the NLDM liberty model define a matrix of two axis (load & trans).
During the placement, there are different optimisation step to fix the DRV (which include the cap & tran, and so one include the fanout).
During the check (PrimeTime for example), after the reports, there are some ECO command to fix the cap & trans, dump the modification in a file and read it back to the PnR tool.

- - - Updated - - -

vcnvcc said:
So rca - Lets consider PT - so all you are saying is first of all check for Max trans/cap, fix it, and then you check setup/hold and fix it?? Am I interpreting it correctly?
Click to expand...
Well by this was you are in very safe side, but if some cap/trans violations could not fixed, you could go to the setup/hold reports.
vcnvcc said:
Now if we go back to DC - Is the same holds true? I know that we'll not fix hold in DC (provided it is not huge) Can you please tell?
Click to expand...
At synthesis step, you cannot control the hold, as the clock tree is not done.
vcnvcc said:
It has to be - you report the setup/hold time for all paths which "don't" have a trans/cap violation....
Can to enlarge it? Thanks..
Click to expand...
No, if you have some cap/trans violations which could not be fixing:
1- you estimate if the violation is huge or not, so the impact on the interpolation to calulate the delay cell, trans value will be over or under estimate.
2- by reporting the setup/hold for the path with cap/trans violations, you will how many setup/hold margin these paths have, and you could said the cap/trans violation related to this path is harmless or not, because if there are so many margin, the error due to the extrapolated timing value is small compare to the margin.
 

 

The example you share is a NLDM liberty file type.
So in your example, the input transition varie from 0.005 ns to 0.44 ns and the output capacitance varies from 0.001pF to 0.523pF.
 

hi rca

please can tell me what are the causes of violation of max cap and max trans


thanks in advnace
 

for max trans: not enough drive to improve the slew.
for max cap, too much routing, or not enough space to split the net.

Why the tool could not fix?
1-no place to add a buffer/inverter or increase the driver of the cell.
2-routing very long which made a important cap, which could be worst with coupling cap, one solution is to apply double space on this net.
3-not allowed to add driver on the net (example:between memory and isolator)
4-Liberty too aggressive
5-misaligned liberty from different providers, misaligned in term of cap/trans capabilities
 
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