11.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFR’s). The SFR’s provide control and data exchange with the CIP-51's resources and peripherals.
The CIP-51 duplicates the SFR’s found in a typical 8051 implementation as well as implementing
additional SFR’s used to configure and access the sub-systems unique to the MCU. This allows the
addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table
11.2 lists the SFR’s implemented in the CIP-51 System Controller.
The SFR registers are accessed whenever the direct addressing mode is used to access memory loca-
tions from 0x80 to 0xFF. SFR’s with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE,
etc.) are bit-addressable as well as byte-addressable. All other SFR’s are byte-addressable only.
Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have
an indeterminate effect and should be avoided. Refer to the corresponding pages of the datasheet,
as indicated in Table 11.3, for a detailed description of each register.
11.2.6.1.SFR Paging
The CIP-51 features SFR paging, allowing the device to map many SFR’s into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFR’s. The C8051F12x family of devices utilizes five SFR pages: 0, 1, 2,
3, and F. SFR pages are selected using the Special Function Register Page Selection register,
SFRPAGE (see SFR Definition 11.3). The procedure for reading and writing an SFR is as follows:
1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).
11.2.6.2.Interrupts and SFR Paging
When an interrupt occurs, the SFR Page Register will automatically switch to the SFR page
containing the flag bit that caused the interrupt. The automatic SFR Page switch function
conveniently removes the bur- den of switching SFR pages from the interrupt service routine. Upon
execution of the RETI instruction, the SFR page is automatically restored to the SFR Page in use
prior to the interrupt. This is accomplished via a three-byte SFR Page Stack. The top byte of the
stack is SFRPAGE, the current SFR Page. The second byte of the SFR Page Stack is SFRNEXT. The
third, or bottom byte of the SFR Page Stack is SFRLAST. On interrupt, the current SFRPAGE value is
pushed to the SFRNEXT byte, and the value of SFRNEXT is pushed to SFRLAST. Hardware then loads
SFRPAGE with the SFR Page containing the flag bit associated with the interrupt. On a return from
interrupt, the SFR Page Stack is popped resulting in the value of SFRN- EXT returning to the
SFRPAGE register, thereby restoring the SFR page context without software interven- tion. The value
in SFRLAST (0x00 if there is no SFR Page value in the bottom of the stack) of the stack is placed
in SFRNEXT register. If desired, the values stored in SFRNEXT and SFRLAST may be modified during an
interrupt, enabling the CPU to return to a different SFR Page upon execution of the RETI instruc-
tion (on interrupt exit). Modifying registers in the SFR Page Stack does not cause a push or pop of
the stack. Only interrupt calls and returns will cause push/pop operations on the SFR Page Stack.