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What is the importance of SFRPAGE in C8051f120?

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prasadsrkrec

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char SFRPAGE_SAVE = SFRPAGE; // preserve SFRPAGE


what is the importance of this in 8051f120 ?
any one explain clearly?
 

It seems to me, from what I read, that the special functions register is pushed onto the stack everytime an interrupt occurs. The data sheet for your processor seems to have alot of information regarding the SFR; I would take a look at it if you are looking for more information. Good Luck.

https://www.silabs.com/Support%20Documents/TechnicalDocs/C8051F12x-13x.pdf
 

The original 8051 family of microcontrollers provided direct access to the Special Function Registers (SFR) through memory addresses 0x80 to 0xFF. However, the additional number of SFRs specific to a Silicon Labs C8051 device and its additional peripherals exceeds the available address allotment, therefore these additional SFRs are managed by a Page system which divides the SFRs into sections or pages still accessible by the same 0x80 to 0xFF address window. Doing so maintains compatible with the original Intel MCS-51 instruction set, while offering the ability to expand the number of SFRs to meet the requirements of a particular device and its peripheral modules.

The C8051F120 utilizes five of these SFR "Pages", the following statement simply save the current context or page number to facilitate returning back to the original SFR Page.

Code:
char SFRPAGE_SAVE = SFRPAGE; // preserve SFRPAGE

By executing the following:

Code:
SFRPAGE = SFRPAGE_SAVE;  // return to saved SFRPAGE

SFRPAGE is simply a register which stores the current SFR Page Number or Context, it is one byte in size therefore the contents can be stored in a single byte type like char, in this case the variable SFRPAGE_SAVE.

For example to configure a DAC module, you would first same the current Page Context, then change the Page Context to the page containing registers required to configure the DAC module, then after the DAC module has accomplished, the saved Page Context is restored as shown above.

Additional information is available in the devices datasheet including a table showing the location of various registers by Page Context or Number:

Reference: C8051F120/1/2/3/4/5/6/7 C8051F130/1/2/3 Datasheet, Section: 11.2.6. Special Function Registers, Page: 136
11.2.6. Special Function Registers

The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFR’s). The SFR’s provide control and data exchange with the CIP-51's resources and peripherals.
The CIP-51 duplicates the SFR’s found in a typical 8051 implementation as well as implementing
additional SFR’s used to configure and access the sub-systems unique to the MCU. This allows the
addition of new functionality while retaining compatibility with the MCS-51™ instruction set. Table
11.2 lists the SFR’s implemented in the CIP-51 System Controller.

The SFR registers are accessed whenever the direct addressing mode is used to access memory loca-
tions from 0x80 to 0xFF. SFR’s with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE,
etc.) are bit-addressable as well as byte-addressable. All other SFR’s are byte-addressable only.
Unoccupied addresses in the SFR space are reserved for future use. Accessing these areas will have
an indeterminate effect and should be avoided. Refer to the corresponding pages of the datasheet,
as indicated in Table 11.3, for a detailed description of each register.

11.2.6.1.SFR Paging

The CIP-51 features SFR paging, allowing the device to map many SFR’s into the 0x80 to 0xFF memory
address space. The SFR memory space has 256 pages. In this way, each memory location from 0x80 to
0xFF can access up to 256 SFR’s. The C8051F12x family of devices utilizes five SFR pages: 0, 1, 2,
3, and F. SFR pages are selected using the Special Function Register Page Selection register,
SFRPAGE (see SFR Definition 11.3). The procedure for reading and writing an SFR is as follows:

1. Select the appropriate SFR page number using the SFRPAGE register.
2. Use direct accessing mode to read or write the special function register (MOV instruction).


11.2.6.2.Interrupts and SFR Paging

When an interrupt occurs, the SFR Page Register will automatically switch to the SFR page
containing the flag bit that caused the interrupt. The automatic SFR Page switch function
conveniently removes the bur- den of switching SFR pages from the interrupt service routine. Upon
execution of the RETI instruction, the SFR page is automatically restored to the SFR Page in use
prior to the interrupt. This is accomplished via a three-byte SFR Page Stack. The top byte of the
stack is SFRPAGE, the current SFR Page. The second byte of the SFR Page Stack is SFRNEXT. The
third, or bottom byte of the SFR Page Stack is SFRLAST. On interrupt, the current SFRPAGE value is
pushed to the SFRNEXT byte, and the value of SFRNEXT is pushed to SFRLAST. Hardware then loads
SFRPAGE with the SFR Page containing the flag bit associated with the interrupt. On a return from
interrupt, the SFR Page Stack is popped resulting in the value of SFRN- EXT returning to the
SFRPAGE register, thereby restoring the SFR page context without software interven- tion. The value
in SFRLAST (0x00 if there is no SFR Page value in the bottom of the stack) of the stack is placed
in SFRNEXT register. If desired, the values stored in SFRNEXT and SFRLAST may be modified during an
interrupt, enabling the CPU to return to a different SFR Page upon execution of the RETI instruc-
tion (on interrupt exit). Modifying registers in the SFR Page Stack does not cause a push or pop of
the stack. Only interrupt calls and returns will cause push/pop operations on the SFR Page Stack.



Does this answer your question?


BigDog
 

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