We got to about the stated efficiency and frequency
on a family of 5V-1V buck ICs using RF CMOS SOI and
using only Coilcraft kit inductors & caps we bought
from Digi-Key, with no "de-embedding of passive
losses" marketing trickery. Just "wallplug". So I think
this can be done with superior switch devices. The
RF CMOS was not very sensitive to fSW, in the
efficiency.
But startup CTOs (in fact startup CxOs of any
function) are by their nature slippery folks and you
should parse carefully anything that's said, and try
to keep track of what's left unsaid. "Forward looking
statements, not to be relied upon". Repeat it to
yourself.
I'd recommend that since the pitch is about aggressive
DC-DC design, you come in with the sensible questions
about how cute theory becomes manufacturable fact.
Be concerned, and slightly knowledgeable, and maybe
they'll figure you can help.
Getting a 12:1 stepdown at 4MHz means you have
about a 20nS on time, and need nanosecond-range
risetimes from the output stage. That's gonna be
some ugly EMI and tough to do current mode control
(expect ringing tails will not be quenched by the time
you're trying to do your current compare). Maybe a
non-fixed-frequency-PWM operating mode could do
better here. But I'd expect mucho ugliness for a more
traditional topology.