joely2k
Member level 1
I am a fresh graduted, just join a semicon firm that working in Layout verification...
As a Layout Verification Engineer, we have to support alot of different Layout tools, Layout verification tools and writing alot of flows, runsets, and automation rules from sypno, mentor, cadence and more....enable to help the mask designers to enhance their productivity...
Besides that, we support and debug alot of DRC, LVS, ANT/NAC, ERC and various other production flows problems and bugs from all kinds of projects.....
AS an LV engineer... what do you all think the career enhancement in future?
Is it good or bad? Thanks... Do guide me.....
As a Layout Verification Engineer, we have to support alot of different Layout tools, Layout verification tools and writing alot of flows, runsets, and automation rules from sypno, mentor, cadence and more....enable to help the mask designers to enhance their productivity...
Besides that, we support and debug alot of DRC, LVS, ANT/NAC, ERC and various other production flows problems and bugs from all kinds of projects.....
AS an LV engineer... what do you all think the career enhancement in future?
Is it good or bad? Thanks... Do guide me.....