[SOLVED] What is the Frequency Response of Delta Sigma ADC

Hello all,


As in title, I want to know frequency response (magnitude AND phase) of delta sigma adc.
(I know there are some but they focus only on magnitude plot...)

I just want examples so any manufactures' delta sigma adcs are OK.

Or if anyone knows how to calculate the transfer function of delta sigma adc, please tell me.
I calculated but the calculation result and the experimental result did not match.


Sincerely,

Yukihiro Hatagishi

The response is the product of the SD modulator itself and the decimation filter. In most cases, you'll only see the decimator frequency response.

You'll basically find two kinds of decimation filters:
- simple CIC decimators with (sin(x)/x)^n frequency characteristic, used with most general purpose ADCs
- FIR decimators with steep roll-off and linear phase, used e.g. for audio converters

The properties of both filter types are described in DSP and SD text books.

Some ADCs have also configurable or programmable filters. Most SD-ADC datsheets are specifying the frequency response.

Dear FvM,

Thank you for your quick reply (I really appreciate you for replying me every time...).


1) about frequency response in datasheet
As I wrote first, I found some datasheets specifying only magnitude plot. Thus I've never seen any phase plots in datasheets.
For Analog Devices : https://www.analog.com/static/imported-files/data_sheets/AD7725.pdf
For TI : https://www.ti.com/lit/ds/symlink/ads1271.pdf

2) About decimation filters
Do you mean a filter composed of 1 stage of integrator and comb by a simple CIC filter??
If so, as far as I calculate the transfer function and from that phase of the filter, I do get linear phase.
Plus, from other documents like wikipedia, I think CIC filter gives you linear phase.
https://en.wikipedia.org/wiki/Cascaded_integrator-comb_filter
As for as I know, additional FIR filters are intended to compensate gain droops but not phase.

3) SD modulation ADC's transfer function
So if the TF of CIC filter is Hcic(z) and that of the analog part is Han(s), the overall TF is
Hcic(z) * Han(s)
right?
(I know I should convert s to z with prepwarps)


Sincerely,

Yukihiro Hatagishi

You are right, CIC filter also have linear phase (symmetrical pulse response). But the same is true for the other FIR filter designs used in ADCs, e.g. AD7725. You'll notice it if you read the datasheet thoroughly. It's completely characterized by the frequency response and a constant group delay.

Dear FvM,

Thank you for your reply.


I am reading the document right now.

Let me go back to my first question.
So whatever the filter is used in the delta sigma modulator, the phase response is linear, right??

I am asking this because my delta sigma modulator realized in FPGA
(I think you remember the post https://www.edaboard.com/threads/298618/) has non-linear phase.
For CIC filters have linear phase, I am wondering if this non-linearity comes from analog part or LVDS or not.


Sincerely,

Yukihiro Hatagishi

Where do you see non-linear phase? I don't see how the problems reported in the previous thread should be related to signal phase.

Dear FvM,


I am sorry for my late reply. I was off for two days.


I did not mention phase delay in the thread. I just meant that the system I am talking right now is on the thread.
Anyway, in the system in the thread, I got waveforms (one is from ModelSim and the other is from my oscilloscope) as attached.

As you can see there is a phase delay.
But what is annoying is that the amount of delay is not same in all the frequency of input...
My guess is that this is caused by CIC filter but I do not get why this happens for as I said CIC filters do have linear phase.

Looks like my question is away from my topic... but please help me out.


Sincerely,

Yukihiro Hatagishi

I must confess that I didn't check if the CIC has exactly linear phase, but I presume it's the case. The SD modulator is however involving an IIR transfer characteristic which can't be linear phase.

Dear FvM,

Thank you for your reply.

The SD modulator is however involving an IIR transfer characteristic

Click to expand...

I have never heard of this although I have been searching about SD a lot...
If you have any documents about it, please give me.


Sincerely,

Yukihiro Hatagishi

Just look at the modulator transfer function. I don't know however if it can explain the observed group delay variations.

Dear FvM,


Thank you for your reply.
I tried to combine the RC transfer function and CIC filter transfer function using bilinear method.
The result is that the group delay is not linear. But it is not far different from what is obtained from experiment.

I think I have to study more about DS modulation.


Best regards,

Yukihiro Hatagishi

If your DSM-ADC is Switched Capacitor type, that is, DT type, it is relative easy to realize STF=1.

However if your DSM-ADC is CT(Continuous Time) type, it is relative difficult to eliminate both magnitude and phase variation over frequency.

See https://www.edaboard.com/threads/301378/

Dear pancho_heboo,

Thank you for your reply.


I think I am dealing with CT type for mine does not have any OP amps or switches.
I only use a capacitor and resistors for my DS.
If mine is CT then why is it difficult?? I thought just converting s to z would work.

BTW, good avatar. I like the comic.


Best regards,

Yukihiro Hatagishi

yhatagishi said:

Dear pancho_heboo.

Click to expand...

No, I'm "pancho_hideboo".
"pancho" is derived from "Pancho Itoh".
"hideboo" is derived from " Hokuto no Ken", https://www.youtube.com/watch?v=8KlHfnHZS2A

yhatagishi said:

If mine is CT then why is it difficult?? I thought just converting s to z would work.

Click to expand...

See page-4 and page-12 of the following.
https://individual.utoronto.ca/schreier/lectures/2012/11-2.pdf

We can easily realize L0(z)=1-L1(z) for DT-DSM.
On the other hand, it is very difficult to realize L0c(s)=1-L1(z) for CT-DSM.