What is the "false lock" in DLL???

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asic_ant

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It seems both the output clock in the correct case and the false lock case have the same frequency and the aligned pahse?
So where on the earth does the "false" happens?
 

As shown in the figure, in the correct case, a clock period is divided by three clock phases; in the false case, two clock periods is divided by three phases. If the clock period is 30ns, the rising edges of \[\phi_1\], \[\phi_2\], and \[\phi_3\] will be separated by 10ns for each in correct case and by 20ns in false case.
 

It's all about the rising edges: in the normal lock case all three rising edges occured between the rising edge of CLK and Test point ..
Maybe this picture will shed more light on this issue ..

Regards,
IanP
 

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