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[SOLVED] What is the error in the following Verilog code of an 8bit ALU

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bihariwa

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This is the 8bit ALU verilog code

Code:
timescale 1ns/1ps
module alu(a,b,s,q);
//input [7:0]A,B;
input [7:0]a,b;
input [3:0]s;
output[7:0]q;
reg [15:0]q;
always @(*)
begin
  if(a>b)
  $display("a is greater than b");
  else if(a<b)
  $display("b is greater than a");
  else
  $display("a is equal to b");
case(s)
4'b0000:begin q=a+b; $display("ADDITION performed:");end
4'b0001:begin q=a-b; $display("SUBTRACION performed:");end
4'b0010:begin q=a*b; $display("MULTIPLICATION performed:");end
4'b0011:begin q=a%b; $display("DIVISION performed:");end
4'b0100:begin q=a&b; $display("AND performed:");end
4'b0101:begin q=~(a&b); $display("NAND performed:");end
4'b0110:begin q=(a|b); $display("OR performed:");end
4'b0111:begin q=~(a|b); $display("NOR performed:");end
4'b1000:begin q=(a^b); $display("XOR performed:");end
4'b1001:begin q=~(a^b); $display("XNOR performed:");end
4'b1010:begin q=(a+1);$display("INCREMENT performed:");end
4'b1011:begin q=(a-1);$display("DECREMENT performed:");end
default: q=16'b0;
endcase

end
endmodule

This is the 8bitALU testbench

Code:
timescale 1ns/1ps
module alu_test();
//inputs, outputs
reg[7:0]a,b;
reg[3:0]s;
wire[15:0]q;
alu a1(.a(a),.b(b),.s(s),.q(q));
initial begin
$display("inputs and outputs are:");
$monitor("time=%t a=%b b=%b s=%b q=%b", $time,a,b,s,q);
end
initial begin
$dumpfile("dumpp.vcd");
$dumpvars(1);
s=4'b0000;
a=9'b10000111;
b=8'b10001110;
#6
s=4'b0001;
a=8'b11111111;
b=8'b11111111;
#6
s=4'b0010;
a=8'b10000101;
b=8'b11111110;
#6
s=4'b0011;
a=8'b10000101;
b=8'b10001110;
#6
s=4'b0100;
a=8'b11001111;
b=8'b11000111;
#6
s=4'b0101;
a=8'b11001101;
b=8'b11000101;
#6
s=4'b0110;
a=8'b01001111;
b=8'b11010110;
#6
s=4'b0111;
a=8'b1110011;
b=8'b10011011;
#6
s=4'b1000;
a=8'b11001011;
b=8'b11111111;
#6
s=4'b1001;
a=8'b01001111;
b=8'b11000011;
#6
s=4'b1010;
a=8'b00001111;
b=8'b1100011111;
#6
s=4'b1011;
a=8'b11001111;
b=8'b11001011;
#6
s=4'b1100;
a=8'b11001111;
b=8'b00001111;
#6
s=4'b1101;
a=8'b11001011;
b=8'b11000111;
#6
s=4'b1110;
a=8'b11011111;
b=8'b11011111;
#6
s=4'b1111;
a=8'b11001111;
b=8'b10001111;
#6 $finish;
end
endmodule

When i am running it on my "Icarus verilog" simulator i am getting following error

alu_code.v:1: syntax error
I give up.

and when i run it on EDA playground i am getting following

[2021-01-13 04:28:51 EST] iverilog '-Wall' '-g2012' design.sv testbench.sv && unbuffer vvp a.out
No top level modules, and no -s option.
Exit code expected: 0, received: 1
Done

please Help me finding mistake.
Thank you for your response.
 
Last edited by a moderator:

timescale needs a back tick in front of it.

`timescale
 
side comment

@ads-ee
is there a usage of timescale that would not need the back tick?

i think a relatively simple "grammar" error like that would be flagged in a more explicit way
or at least the line where the error occurred (or where a problem was recognized) would be provided.
 
Besides giving a line number It also says it's a syntax error, which it is as timescale is not a Verilog keyword (it is a compiler directive).

If you use Systemverilog you can instead use timeunit and timeprecision, which are SV keywords.
 
Yes it solved the problem. Alongwith that there was one more error in testbench, i mistakenly typed 'b' as 10bit binary number instead of 8 bits.
Also, Can you guys please suggest if there is a way to convert C program into Verilog HDL somehow?. Thanks
 

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