[SOLVED] what is the difference that can be seen in LVS runset file and DRC runset file

[Chaos89]

hello!

can any one please explain me the difference between LVS runset file and DRC runset file in ASIC design Physical Verification?

In detail what to be observed if we are provided with the two runset files ?

any images or snapshots are accepted for better understanding.

thanks

 

[erikl]

DRC rules' files (as the most important parts of the runset) define the min. or max. dimensions of polygon structures for all single layers, and the min. or max. spacings between polygons on the same or on different layers, respectively min. or max. overlapping dimensions of these. Other rules check for polygon corners not sitting on grid points. Max. and min. total coverage percentage of many layers will be calculated. Another rules' file set checks for max. connection area to (temporarily) unconnected MOSFET gates during (and at the end of) the fabrication process, poly- and metal-by-metal layer-wise (antenna rules). All these rules' sets serve as to hinder violations of the fabrication process, or to enable/disable required/undesirable physical or electrical interactions.

LVS rules' files (again: as the most important parts of the runset) try and detect ("extract") the context between layout structures and primitive devices, concluding this from the combination of layer dimensions and combinations of these laid down in the rules' file. Moreover, serial and parallel connection of similar devices must be recognized. Also, the connectivity between recognized devices will be detected by connectivity rules which define the connectivity between the primitives' nodes by knowing the connection through conducting layers, vias and contacts. This achieved, an extracted netlist can be constructed. For the schematic, a similar - but much simpler - process creates a schematic netlist.

Recognized nets between nodes will be ordered by the number of node connections per net, and by knowing the number of node connections per primitive device per net, by comparison with the appropriate schematic netlist the software tries to find a 1:1 match between the layout and the schematic netlists. Corresponding designations of node and pin names can help a lot for success and/or shorter run-time, especially for highly symmetric structures.