In verilog file, I can't make clear of the keyword parameter and define,
that is to say, in the course of synthesis, which circuit the 'parameter' create and which circuit the 'define' create?
Thanks for any advices
clivechen
Re: what is the difference of parameter and define in verilo
Define in verilog is used to write MACRO's whereas parameter is used where
you want to use constant or you want to make some parameter parametarizable!
`define is used for global parameterization whereas
parameter is generally used for local parameterization.
Synthesis of `define and parameter will depent on the context in which they are used!
Hope this helps you!
Re: what is the difference of parameter and define in verilo
a `define if a global macro. It work exactly like a #define in c/c++. `define is of global scope. If you define in a module, it still stay declared after the module.
On the other hand, 'parameter' is local to a module. It is used to define a property of the module. This property can be left to default, or can be modified at instantiation of the module. For example
Code:
module simpleadder(a,b,sum)
parameter width = 8;
input [width-1:0] a;
input [width-1:0] b;
output [width-1:0] sum;
assign sum = a + b
endmodule
By default, the adder is 8-bit (the width parameter use the default assigned value of 8). However, the instantiator module can change parameter value.