clivechen
Member level 3
In verilog file, I can't make clear of the keyword parameter and define,
that is to say, in the course of synthesis, which circuit the 'parameter' create and which circuit the 'define' create?
Thanks for any advices
clivechen
that is to say, in the course of synthesis, which circuit the 'parameter' create and which circuit the 'define' create?
Thanks for any advices
clivechen