What is the difference between Unsigned and Signed counter?

Hi
my doubt is wht is the difference between Unsigned and Signed counter.

Re: counter doubt

signed counter has a separate sign bit while unsigned doesnt....

Re: counter doubt

I reckon nothing, yes I dont think there is any difference. It depends upon how u are using a count. For example, a simple 4 bit counter can be treated as a -7to+7 twos compliment(signed) counter or a 0to15 unsigned counter.
Or you can simply have a dedicated sign bit as suggested by Mr Srinivasan. But then an up counter would actually be a down counter when the sign bit says its a -ive count.
Let me know where do you want to use it, and i would be able to offer some more help. As Mr Srinivasan has also given a way to do it, you may want to choose either.

Re: counter doubt

hi thanks for response:
actually iam going thru docs of xilinx and i found terminology of unsigned counter and signed counter but the code written is same except the library included.

here is the code:
-- 4-bit Signed Up Counter with Asynchronous Reset
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity counters_7 is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counters_7;
architecture archi of counters_7 is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi



--
-- 4-bit unsigned up counter with an asynchronous clear.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counters_1 is
port(C, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counters_1;
architecture archi of counters_1 is
signal tmp: std_logic_vector(3 downto 0);
begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;

Re: counter doubt

The inclusion of libraries(unsigned/signed) dictates the way a binary number is interpreted in the design unit.
Take a 4 bit binary number say, 1010: what this number is equal to?
its equal to decimal 10 if std_logic_unsigned is being used;
its equal to (-6) if std_logic_signed is being used.

See, then there is no difference between implementation of a 'signed' or an 'unsigned' counter. its just how u interpret the count. In your case its being interpreted in two different ways using two different libraries i.e std_loigc_unsigned, which makes it a unsigned counter, or std_logic_signed, which makes the same counter signed.
Hope it helped.
Kr,
Avi
http://www.vlsiip.com

Re: counter doubt

Because of the use of 2's complement, unsigned and signed counters are the exact same circuit.

The difference will appear when the counter outputs are compared (<, <=, >, >=) in the same architecture.