To extend a little bit (or to give examples of checks) on what erikl already explained:
* LVS (Layout Versus Schematic comparison) - does the following things:
- net connectivity extraction (determines the connectivity between the polygons)
- device recognition (identifies the devices - like MOSFET, design resistors, design capacitor, diodes, etc.)
- layer derivation (for example, calculates gate poly and field poly layers from poly and active layers)
- cross-referencing between schematic and layout
- calculates layout-dependent instance parameters for device instances (such as gate width and length, area/perimeter for source/drain, well proximity effect, LOD effect, etc.)
- etc.
* DRC (Design Rule Checking) - checks various rules, such as:
- metal line widths
- spacings between different layers
- metal density
- etc.
(in modern technologies there thousands or tens of thousands of such rules)
* ERC (Electrical Rule Checks) - verifies various things related to electrical behavior:
- resistance rules (e.g. resistance from a pad to ESD diodes, from ESD diodes to power clamps, resistance to guard rings, etc.)
- current density rules (ESD current densities, etc.)
- voltage polarity checks (for example - checks that one of the parasitic diodes are forward biased)
- voltage domains checks
- latchup checks
- etc.
Max