Re: Latency and delay
The place where 'latency' and 'delay' become significant terms is in the physical design of your clock distribution network.
Before the clock distribution network is implemented (i.e. all steps up to and including placement), the clock distribution does not exist and is purely abstract. The clock signal is assumed to magically arrive at all the clock pins at the same time (with some uncertainty). This is called "ideal clock mode".
Once the clock network is actually created (usually with clock tree synthesis (CTS)), the clock signal can actually be timed exactly as it propagates from its source through a tree of buffers to every flip-flop. This is now called "propagated clock mode".
"Latency" is the term used to describe the delays on the clock distribution in ideal mode. There are usually 2 latencies that can be defined: the source latency and the network latency. The source latency is the delay specified to exist between the true source of the clock signal and when the lock signal arrives at the root clock pin in the design (so the true source is off-chip somewhere). This is used to specify the phase relationship between two clocks on the chip.
Network latency is the specified clock signal delay from the root clock pin to the flip-flop clock pins. This is not a measured delay - it is simply specified as part of the clock definition.
And so, "delay" in a clock refers to the actual measured delay in propagated clock mode. Source latency does not change when you build the clock - it always remains 'ideal' because it is off chip. The network latency, however, gets replaced by the "insertion delay". This is the actual, measured delay from the clock root to each individual flip-flop (usually it refers to the average insertion delay over all the FFs in the clock tree). Most CTS tools accept the network latency to be the desired insertion delay target that must be met. In the bottom-up design style, the network latency is often not specified or set to zero. This means the tool should do the best it can.