Physical compiler does placement and synthesis at the same time, while DC only does synthesis and estimates the wire lengths based on wireload models that you provide (which are usually based on module size).
Because physical compiler uses actual placement information to figure out the wireloads, the timing of your final design will closely resemble (as long as you don't later run into routing problems) what the physical compiler has produced. The netlist produced by DC, on the other hand, will probably need lots of massaging by the p&r tools to achieve the same timing results.
The downside, of course, is that DC runs a lot faster, because it doesn't case about cell placement.