Re: Delta Delay
Hello,
I have an advance question about delta delay.
I've developed a circuit in VHDL which does only contain combinatorial logic with an (unavoidable) internal feedback. In simulation it happens that the output signal needs 3 delta delays to stabilize.
time x+1: '1'
time x+2: '0'
time x+3: '1'
with "time x" as simulation time + delta delay. During the second delta delay my output signal has the value '0' which I don't want to have. Has somebody an idea what happens with this circuit when it is synthesized? Will the circuit operate correct or will the output signals contains this pulse from the second delta delay?
Thanks for your help!