shady205
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Hello friends..!
I have some doubts regarding DAC. I need to design a 8-bit parallel input DAC.
In the specification i have been given Update cycle as 10 Hz ~1 Hz, CLK input signal is 0.1MHz, and DAC control logic CLK frequency as 0.1MHz.
How this signal is diffrent from Sampling Signal.
Can anyone tell me how they are related if not ... tell me how is it related to other parameters like INL DNL Power .....Any parameter..
Thanks in Advance
Shady205
I have some doubts regarding DAC. I need to design a 8-bit parallel input DAC.
In the specification i have been given Update cycle as 10 Hz ~1 Hz, CLK input signal is 0.1MHz, and DAC control logic CLK frequency as 0.1MHz.
How this signal is diffrent from Sampling Signal.
Can anyone tell me how they are related if not ... tell me how is it related to other parameters like INL DNL Power .....Any parameter..
Thanks in Advance
Shady205