What is the best way to create a new vector of size Nbits in VHDL?

[pixel]

I need to create new vector of size Nbits where most sinificant bits are filled in by
A(4). What is the best way to do that?

A: in STD_LOGIC_VECTOR(4 downto 0);
B: in STD_LOGIC_VECTOR(Nbits-1 downto 0);

This works only if I know Nbits
B=(A(4)&A(4)& .... A(4)&A(4)& A)

 

[FvM]

Re: VHDL question

The most flexible way is by a FOR loop, either in a process or as a FOR GENERATE.

BitGen:
FOR I IN 4 TO NBITS-1 GENERATE
B(I) <= A(4);
END GENERATE;

or
PROCESS(*)
BEGIN
FOR I IN 4 TO NBITS-1 LOOP
B(I) <= A(4);
END LOOP;
END PROCESS;

There is also an assignment syntax with a combination of OTHERS and designated bits, but I generally don't use it.

 

[achandra]

Re: VHDL question

Is a statement like B=((others<=A(4))&A); supported?

 

[FvM]

Re: VHDL question

These two syntaxes are possible:

B<=(nbits-1 downto 5 => A(4)) & A;

B<= (others => A(4),3 => A(3), 2=>A(2),1=>A(1),0=>A(0));

 

[pixel]

Re: VHDL question

Danke schön FvM,
Does verilog have equivalent to "others"?

 

[FvM]

Re: VHDL question

Verilog has no construct adequate to VHDL aggregate that was used in both examples. The expression can be written using concatenation and replication, also utilizing nbit as a length parameter.