What is the best tools to simulate PLL?

[flyinspace]

nanosim pll

I think the Hspice is to slow to analyze the transition analysis.
Someone told me to use the behavior model such as verilog_ams to simulate the PLL.
But I think the precision is not good.
Do you believe which EDA tool more adapt to do it?
Thanks.

 

[bjh1004]

matlab code for pll mit

hsim from nassda or nanosim from synopsys is good for
fast simulation.
(Accuracy is about 90 - 95% of hspice.)

 

[dll_embed]

I used simulink for my PLL function simulation. It is quite fast. But not sure whether the accuracy can meet your requirement. If you are talking about a PLL chip, then the one provided by vendor should be more useful.

 

[flyinspace]

My project is to design the analog PLL in cmos process.
Who can tell me where can I find some articles or tips to simulate the behavior function of the PLL in nanosim?
Can the spectre in Cadence do the same work?
Thanks a lot.

 

[RF_beginner]

you can go to AD'S OR NATIONAL SEMICONDUCTOR'S web where maybe you can get you want

 

[eltonjohn]

Hi friend .. I had latly to simulate a feedback system very close to a PLL
With motor witha tachometer intead of a VCO .. ( the functionality is the same.. pruduces a frequency controlled by voltage ).
I got the VHDL-ams sources of a PLL and i modified it .. Then used simplorer 6 .. but smash can also be used.. If you need the vhdl-ams
sources PM me

Regards

 

[nativeda]

Refer to Cadence's SpectreRF User Guide, Appendix "An Introduction to the PLL library". With the behaviroal model it provided, you can evaluate your design in seconds.

 

[talap]

Try SystemView
It is a good tools

 

[andy2000a]

hsim / nanosim / aditspice is fast than hspice , but I ever try it

I find no initial state , 3 tool have difference locking time , and hspice will "un_lock" (postsim include many RC ...) on worst case MODEL

who can provide matlab simulink code about PLL model ?

I am learn simulink know , but I want to get some simulink model examples like delta_sigma, ADC , PLL ...
becuase some book only "control system/DSP examples no circuit example"

thank you

 

[panpan]

Maybe you could try ADS. You can do "envelop" analysis in ADS, by which you will get the time domain and frequency domain perfomance quickly and synchronously.

 

[Igor_S]

I have seen the beuttful tool for behavioral PLL simulation from MTI.
Try https://www-mtl.mit.edu/~perrott

 

[khouly]

i think @dvance MS of mentor graphics is good in mixed simulation
u can simulate in VHDLAMS with Eldo , so u can simulate the analog parts of PLL with eldo and the digital using VHDL , " divider"

i saw it , i think it will save much time , and give a very accurate results

 

[sutapanaki]

Hi,

I did simulations an year ago on my pll, both ac and transient. I used Eldo for both of them. To simulate the ac behavior of the loop I created a model from the real schematics of the pll but with ABM blocks. To verify that it matches well to the transistor-level schematics I did the same transient simulations on both of them and checked how well they overlap. The transient simulation of the schematic level PLL takes a long time. It is better if you can use Linux instead of Unix for that.

 

[rfsystem]

Most important is to think about the modelling strategy. If you have to simulate a -60dBc spur effect from the charge injection or a noise level -90dBc from the sigma-delta you require time steps in the range of ps. With settling times of 50us you get about 10-50e6 time steps. That is really hard also for medium size 1-5k analog simulation.

Independ from what you use as simulation engine try first to model the component behaviour in the phase domain. So the simulator is time discrete in the phase domain. Matlab would be the best choice. But also VDHL-AMS or Verilog-A fits.

If you working in the time domain you could model the VCO/Divider as an edge generator. It integrates the VCO voltage and places an edge if some Vs level is reached. So you avoid all other edges or time steps in the VCO/Divider. The VCO/Divider should be verified before.

 

[goodboy_pl]

for system level simulation, matlab, simulink and @DS are normally used.
matlab and simulink are alittle slow. u can translate matlab codes to C and compile it to have faster runing algorithm.
A@DS have several samples and uses AC, transient and envelope simulation for system level.
all of mentioned method have their approximations for example when u simulate the PP_PLL loop with AC analysis u assumed that the loop is not so wide band and the resistor of the filter is not so large other wise the simulation result will be incorrect!
also for matlab and simulink simulation time step must be selcted wisely, otherwise the jitter due to mathematical errors in time variable affects real response of the loop.
for transistor level simulation use @DS (specially for GHZ range LC tank osc.), cadence IC and HSpice.

BTW, simulation of mixed signal ckts like pll requires alot of time and proccessing power for example transient simulation of a pll may takes 24 hours on a P4 2400MHz!

one important comment:
first start with system level simulation to find system and block specs then go to transistor level sim of each block to meet the requires specs.
DO NOT CLOSE THE LOOP BEFORE SATISFYING THE SPECS OTHERWISE U WILL CONSUME YOUR TIME!!!

BEST!

 

[gerryhsu]

Hspice is very accuracy but ut will take forever to simmulate the PLL. Use Hspice to simmilate the Oscillator only. For the whole circuitry simmulation use fast spice simulation tolls such as Starsim , Hsim or nanosim. Most of these tools have modeoptions which allow you to set the accuracy for sub-blocks. With these to ols you can simmulation PLLL in less than an hour

 

[AXE]

this depends on which level u want to simulate

 

[tlihu]

Any recommendation on setting the accuracy for ecah building blocks such as pfd, vco?

 

[hmsheng]

You can try @DS

 

[egemini]

Hello we use Natioanl WEbench.
I think its good.