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What is the best architecture for adc with 10bit 80ms/s?

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m_mosazadeh

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arthitecture for adc

what is best arthitecture for adc with 10bit 80ms/s?
 

Re: arthitecture for adc

Maybe Subranging or folding or mixed one.
UCLA Dr. Abidi group tried Parallel Pipeline in early 90's, I guess.
Simple pipeline, even with some caribration techniques to enhance a resolution, cannot achieve such a high speed.
 

Re: arthitecture for adc

i did pipelined ADC with same specs..and its working fine..
whts ur power spec..
 

Re: arthitecture for adc

The ADC is very low power .I want to use pipeline with SAR instead of flash because of low power consumption.DO you have any idea?
 

arthitecture for adc

U can find many papers with almost the same spec use pipeline architecture.
 

Re: arthitecture for adc

I think SAR ADC cannot achieved such too high speed due to its recursive operations. And in this range the most suitable ADC should be pipelined (or parallel pipelined ADC). I don't know how low for your power specification, but at 10 bit 80MS/s I think at least > 60 mW.
 

Re: arthitecture for adc

infact 30mW is the latest power number for 10bit 80MHz Pipelined ADC..
SAR can be used as SUB-ADC but u will not be able to get ur speed spec..
If u want i can refer u a paper..
c ya
Opamp741
 

Re: arthitecture for adc

reltol1 said:
Maybe Subranging or folding or mixed one.
UCLA Dr. Abidi group tried Parallel Pipeline in early 90's, I guess.
Simple pipeline, even with some caribration techniques to enhance a resolution, cannot achieve such a high speed.

Sorry, I was behind..... Many papers about high-speed pipeline have been published.
 

Re: arthitecture for adc

Although many papers published in IEEE, but how many ADC are suitable for real production without low yield ?
 

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