What is th difference between pre and post layout STA...?

[giggs11]

I understand that STA before P&R is meant to highlight the crtical paths of the design for corrective actions and also give an estimation of the delays. These delays are formulated through the accounting of standard cell delays and wire delays.

However, how is post layout STA different form this. Is it because of the addition of buffers in the Clock Tree Synthesis.

 

[wadaye]

Re: What is th difference between pre and post layout STA...

I understand that STA before P&R is meant to highlight the crtical paths of the design for corrective actions and also give an estimation of the delays. These delays are formulated through the accounting of standard cell delays and wire delays.

However, how is post layout STA different form this. Is it because of the addition of buffers in the Clock Tree Synthesis.

You do STA post-layout because you have extrated-parasitics and sdf, so

you don't need the inaccurate WLM to estimate the cell & wire delay. And

you can use real clock post-layout.

wang1

 

[gaonkc]

pre layout sta is the fornt-end netlist sta .
post layout sta is the back -end netlist with sdf file sta

 

[skymusic]

The most difference is wire delay calculation. Normally, at the pre layout stage, use wire_load_model provided by library vendor or extracted by ourselves to calculate the wire delay. At the post layout, first the net RC parameter is extracted to calculate the wire delay, at the same time, according these RC, get the load of cell's output. So the post layout STA is more accurate.

 

[Arthurzss]

The post layout STA is more important.
It is more accurate to your IC to tape out.