What is soft connection in layout?

[ee484]

What is soft connection in layout??

Thanks

 

[vipin_vasudevan]

softconnection

Hi ,
Soft connections are mainly the connections which is made thro diffussioons.Some times people may calll the same for label short ( x also.
Rgds
Vipin

 

[Brittoo]

what are soft connections

hi ee484

Let me explain you this concept with an example.When you have 2 backgates( bulk) on the same net left unconnected, it would result in 2 different nets rather than 1, softconnection occurs. Make sure the pins are connected and the connection is completely done.
Also, in a nfet, when the Source and backgate are shorted and you are connecting them to a different net rather than Gnd, you would need to isolate this backgate from the substrate. In this case, a DNW is required. Else, we come across soft connection again.


Regards
Brittoo

 

[ee484]

what is soft connect in lvs?

How about the case where pmos bulks are connected to the source terminal?
Is this case supposed to give me soft substrate pin error?
Thanks

 

[rfsystem]

softcheck nwell connections

Depend on what you called allowed.

Typical the bulk currents, dynamic or static are low relative to the others. So a softpath back to the source connection is aceptable.

So the role softconnection of bulk to source is reasonable.

I remember that Calibre have unidirectional rules. So it allows connectivity from bulk to source or dain diffusion but not from diffusion to bulk. So a softconnection

P+ NWELL P+

is not connected in the extracted netlist. So a separate ERC run is not required. Violation is shown in the LVS.

 

[qutang]

soft,connection

using text connect two port.

 

[Brittoo]

soft connection lvs cadence

hi ee484

In my opinion, the case that you have pointed out should not give any softcheck errors provided the Pfet source is connected to the right potential. In case of nfets, it is a major concern as the substrate forms the floor for all the devices and hence to isolate that particular nfet, a Deep N welll is required.(pfets are already in the nwell).

 

[leohart]

what is soft connect

hi ee484


Also, in a nfet, when the Source and backgate are shorted and you are connecting them to a different net rather than Gnd, you would need to isolate this backgate from the substrate. In this case, a DNW is required. Else, we come across soft connection again.


Regards
Brittoo

hi，dose this mean when we use a process which do not have DNW，we cannot use nfet with its s and b conneted together to a potential other than gnd？Or we will get a softconnection with psub connected to gnd and another potential at different place.
But I don't see any problem with this softconnection?If the two connection are apart far enough.The resist of the sub is so high...

 

[pvnk]

soft connection error

even if they are far apart, because of the tool algorithm/rule file, tool will catch it. if your team is confident about the consequences, you can ignore it. but that will not be a good practice.

But i'm not clear what to do if we dont have a DNW. i think avoiding backgate ties to source will be a better option. because, if you stamp same substrate to two different potentials, there exists a chance to draw current in on of these junctions.

thanks

 

[Brittoo]

softcheck erc

Hi leohart

In most of the processes that i hav worked on, there was either a DNW or a areaid layer( a virtual layer used just to differentiate the respective nfet from the rest of the substrate). Apart from this if there are any other ideas to avoid this softconnection error, i would definitely like to know as i have faced this error in the case of nfets havin S and B connected to a different potential from Gnd.


Regards
Brittoo

 

[pvnk]

calibre softconnect debug

ahh yes the area id techniques will fool the tool. it's just like ruling out the error. but in practical it'll not solve the issue ( DNW do). but i've seen tape outs with this areaid technique. it all had worked fine on silicon!

 

[Brittoo]

soft connect lvs

Hi pvnk

So u think there is nothin else that can be done apart from DNW and areaid techniques??

Regards
Brittoo

 

[pvnk]

soft connect layout

I think, putting a substrate guard ring around such fet can give a better isolation. i personally do that.

 

[Brittoo]

soft create connection

Hi pvnk

Could you plz explain how its gonna help in case of nfets with S and B connected to different potential from Gnd as substrate is still the same.

Regards
Brittoo

 

[pvnk]

what is soft connect?

My idea here is, this guard ring will cut a shallow trunch isolation for that locality of substrate. generally the resistance of deep substrate is higher ( at least that's my knowledge.) it'll thus reduce the possible leakage current.

 

[srieda]

nfet in nwell lvs

As far as I know, soft connections are connections done through texts in order to tell the LVS tool to connect them. However this means physically there are no connections as of yet. The texts are named with a ':' and hence this method is also known as "colon connect".
I am a designer and hence layout guys, plz correct me if my understanding is wrong... :|

 

[leohart]

soft connect

hi, I think only cmos process with more advanced features has DNW, DNW are used to isolate some sensitive fet from noisey sub in mixed mode design.Definitely Generic NWell or Twin Well process won't have such DNW things...(Correct me if I'm wrong )
And the area id layer is just tell DRC and LVS to forget about the softconnection stuff...It dosen't really solve this problem

ps:Most analog students were told to always connect the backgate of nmos to gnd in nwell process,and vice versa when you use a pwell process. I don't see why to connect the b and s then to a different potential?I know this could reduce the body effect,but normally this was used in disceret mos design?

 

[gafsos]

Re: Soft connection??

Hello

A “soft connected” node is one that has been connected through a nonrouting layer (Figure).
Nonrouting layers are usually identified as such because they are highly resistive and result in poor circuit performance.

Typically, active and N-well layers are not routing layers, but it is still
possible to inadvertently use these layers to make electrical connections. The
problem with this is that the DRC and LVS will pass, but the circuit performance
will be poor. Only a very detailed layout extraction and simulation will
find this type of “soft” error.

Typically, this type of work is not practical, so a correct-by-construction approach is taken to avoid this effect.

Figure shows two examples of soft connections. The N-well example shows how a transistor is electrically connected to VDD, but the signal path flows through N-well as part of the connection.

The second example shows how the transistor performance may be compromised by a connection to the drain that is not completed in metal. In this case the single contact does not help in any way, and an equivalent layout would be one without it.
Special checks built into the layout verification process can help to
identify these problems; however, they are difficult to debug, and it is best
to simply avoid making the error in the first place.

Wish tha's clear
gafsos

 

[pvnk]

Re: Soft connection??

ps:Most analog students were told to always connect the backgate of nmos to gnd in nwell process,and vice versa when you use a pwell process. I don't see why to connect the b and s then to a different potential?I know this could reduce the body effect,but normally this was used in disceret mos design?

I think in some cases like in an opamp, if you take the bulk to sourse, it'll give a better bandwidth. that's where this whole issue will pop up. I've seen designers doing this.

 

[srieda]

Re: Soft connection??

Is this different from the 'colon connect' feature that I have talked about?