I would just like to add to alam4vlsi.
Understand this : The chip has various metal layers. In our consideration let us take 6metal layers. Let us assume M1,M3,M5 are used for horizontal and M2,M4,M6 for vertical. Each of them have several tracks, i.e virtual lines on which the copper interconnects could flow once the chip is fabricated. Let us assume that for a chip of die (3000X3000 um) we have 15000 tracks for each metal layer (0.1 width and 0.1 pitch).
What happens during routing is this :-
1> In global routing the aim of the tool is to just assign the nets (which are declared in verilog/netlist as wire) to the metal layers with minimum deviation and avoiding long straight routes etc.. It has a very basic objective-Make sure that all the layers can accommodate the routing given the congestion and area might sometimes not be sufficient to accomodate all wires. In such cases floorplan would have to be changed.
2> If global route is pass and H and V congestion on the metal layers is not huge then we understand that there will not be many DRC violations and we go ahead with the track asignment. Track assignment is assigning tracks out of the 15000 tracks on metal layer to some net. That ways the resources are allocated. Please do not think that one track is for one net only. It is for one net only in one co-ordinate, it could be for some other net in some other co-ordinate. Track does not mean the physical wire, it is just a guide.
3> Detail routing is like differentiation. It will break t whole die into small pieces called SBox and then for each SBox it will complete the routing and minimize he DRC ( spacing, notch etc...)
You can call a route a good route by looking at these 3 things basically:-
1> DRC violations
2> Timing after SPEF extraction (especially SI for long nets)
3> Congestion for each metal layer
Ro9ty