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A post layout simulation is usually done to verify the design actually works after the layout. After layout, we notice some important parasitics.,like in a wire, noise injection in the substrate, the actual matching and the actual component values.
So, you extract the netlist from the layout(in some cases, get the RC extracted netlist) and then run the simulations. In this way, you are more guaranteed that your design works in Silicon
Though I believe the RC extraction is calibrated for under 1MHz or so in most foundries. So for high speed circuit even with RC extraction the simulation may be way off the measured result. But it is nevertheless a good verification. So overdesign is a must !
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