Hi Bjtpower,
The output of some logic gates is designed to either sink the current or source it. It can do only one of these two. For example, consider a common-source stage with an n-MOS transistor which has a load resistance RL. You can assume this to be a NOT gate. If you apply vdd to the gate of this transistor, it can make the output transition from high to low; however, the transistor itself cannot make the output go to vdd. This second action is achieved by means of the RL. Since some times this pull-up resistor is not included inside the chip (microcontroller, a simple logic gate, or whatever) and the drain of the transistor is open, that's why they call it an open-drain configuration.