what is meant by virtual clock definition and why do i need

[arjun1110]

virtual clock

Hi

what is meant by virtual clock definition and why do i need it?

Regards.

 

[tariq786]

virtual clock design compiler

I am sure i read why do one needs virtual clock by going through design compiler workshop.



Let me know if you cant download.

 

[shelby]

virtual clock definition

For paths going through a primary input port, the tool needs to know the frequency of the clock driving the signal in order to create a proper timing path. Similarly for output ports, the tool needs to know the frequency of the flop capturing the signal.

This is why we define a virtual clock. To give a clock relationship to paths going through IO ports.

 

[arjun1110]

need for virtual clock

Hi Shelby,

Thanks for you precise answer to my question.

Also I have posted one more question regarding timing.

The question is, I have closed STA with SPEF in PT/PTSI and When doing back annotation with SDF I am seeing functional failures. What mignt be the reason.

This was the question asked in the interview.

If you know the answer please share with us.

Regards.

 

[shahal]

what is virtual clock in sta

I knew this before but I am drawing a blank now.. so why not use a real clock to constraint the IO instead of using a virtual clock?

 

[shelby]

asic virtual clocks

@arjun
1) bad timing constraints (false path in STA on a real path)
2) asynchronous logic that STA would not catch
3) missing xfilter on synchronizer
and probably many more ...

@shahal
real clock constraints are defined at a clock generation point inside the design. IO signals are launched/captured by clocks outside the design, which is why we define virtual clocks. If the clock also goes through the IO you may be able to define the clock as real at the IO port, but this may not always be the case.

 

[arjun1110]

why we need virtual clock

Thanks Shelby.

I am clear now.

Regards,

 

[jaydip]

Shelby,

we can use set_input_delay and output_delay constraints with respect to actual clock, why do we need virtual clock to define it? I mean. thats how we do, is it not? i am not clear why do we need virtual clock ...

 

[jasonkee111]

Re: asic virtual clocks

If the clock also goes through the IO you may be able to define the clock as real at the IO port, but this may not always be the case.

i am a bit confusing here.

Question:
1. The clock you mean is the clock send from other chip or oscillator?
2. Does the clock go through the general purpose IO or dedicated IO pin?
3. If the clock from other chip feed into IO, we don't need to use virtual clock?