[SOLVED] what is maximum speed of chipscope signals

[rocking_vlsi]

Hi

1) What is the maximum speed at which we can watch Flip-flop value changing through chipscope ?

2) what is the maximum number of different signals we can watch through chipscope ?

3) What protocol does chipscope uses to communicate between ILA, ICON, VIO and system.

I have XUP Virtex 2 Pro board. Please suggest any tutorial which will give idea about above three questions.

Thanks in Advance.

 

[TrickyDicky]

1) there is no maximum speed - it will depend on your design and routing resources.
2) It depends how much memory is available in the device. Often, a longer capture window means you can view less signals.
3) That will be proprietary and I dont think XILINX will tell you what it is.

 

[rocking_vlsi]

Thanks Tricky

Can you send me any tutorial with example where I can capture fast changing output signals on chipscope.

 

[TrickyDicky]

how fast changing are you talking about?
usually you just use the same clock as the "fast changing" signals. You can use a faster clock if you need to, but you're never going to see it perfectly.

 

[rocking_vlsi]

Suppose i have 8 flip flop outputs changing at speed of 25MHz... Can i capture 8 bits consecutive from each flip-flop.

 

[TrickyDicky]

then you just need to set the sampling clock to the same 25MHz clock.

 

[rocking_vlsi]

Thanks...

How to set Sampling clock ? Is it available in chipscope manual...

 

[TrickyDicky]

If you instantiate chipscope core in your HDL, you just connect it to the clock port.

 

[rocking_vlsi]

thanks... i have tried just 4-bit counter... it is simple... got to know...

 

[rocking_vlsi]

hi

i want to know ..
at what speed the chipscope samples the data....
what clock frequency chipscope core uses....

 

[j_andr]

at what speed the chipscope samples the data....
what clock frequency chipscope core uses....

as TrickyDicky said - chipscope uses the clock you've connected to it;
you can connect any clock of your design you wish;

chipscope is just a module - same as a module written by you,
but 'prepeared' by an fpga vendor;
so it's up to you what signals this module monitors and with
what clock it runs;
also the max. chipscope clock frequency depends - as in 'normal'
design - on complexity of the whole project, your logic + the monitoring logic;
[the chipscope]
---
J.A

 

[xtcx]

1) What is the maximum speed at which we can watch Flip-flop value changing through chipscope ?

I'd say it is directly proportional to your flipflop clock. If you use 300MHz clock, you can watch flipflop value changing at 300MHz rate. No doubt.

But remember, that this is true only for synchronous designs. If you want to capture asynchronous signal namely asy_sig, say at 2MHz, then your sampling/trigger clock shall be at aleast 20 MHz to watch asy_sig toggling. Otherwise, you will miss the exact edges of asy_sig.

But this is yet not accurate. Instead you can keep rising edge trigger of asy_sig and then capture the signal for good timing results.

The higher the trigger clock, the better the waveforms.