What is Max Frequency of the commercial ASIC u hav designed?

• Feb 26, 2005

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eda_wiz

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What is Max Frequency of the commercial ASIC(std cell based) that you have designed?
Please also tell , which was the application and which process,fab you used?

rgds

 

• Feb 26, 2005

• #2

omid219

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133 MHz, Poweline networking, .18u TSMC

 

• Mar 1, 2005

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mic_huhu

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Re: What is Max Frequency of the commercial ASIC u hav desig

82M Hz

 

• Mar 1, 2005

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sunms

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2.5GHZ, serdes, 0.13 ST

 

• Mar 1, 2005

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shelkerahul

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Re: What is Max Frequency of the commercial ASIC u hav desig

180 MHz in 0.13u TSMC

 

• Mar 1, 2005

• #6

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marksile

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Re: What is Max Frequency of the commercial ASIC u hav desig

200 MHz in 0.18u

 

• Mar 1, 2005

• #7

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wangkl

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Re: What is Max Frequency of the commercial ASIC u hav desig

266MHZ worst case
400MHZ typical case
0.13u MOT

 

• Mar 1, 2005

• #8

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minhle

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Re: What is Max Frequency of the commercial ASIC u hav desig

205Mhz CMOS090 Arm core

 

• Mar 2, 2005

• #9

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eddsos

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Re: What is Max Frequency of the commercial ASIC u hav desig

100MHz for RAM access.

 

• Mar 2, 2005

• #10

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eda_wiz

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Re: What is Max Frequency of the commercial ASIC u hav desig

sunms said:

2.5GHZ, serdes, 0.13 ST

Click to expand...

2.5GHz clock with .13u process !!!!!!!!!!!!!!! Really?

 

• Mar 3, 2005

• #11

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atremp

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480M USB 2.0 PHY

 

• Mar 3, 2005

• #12

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ryang

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200MHz, .18u UMC

 

• Mar 3, 2005

• #13

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dolby.yang

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Re: What is Max Frequency of the commercial ASIC u hav desig

250MHZ,0.18

 

• Mar 3, 2005

• #14

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Silicide

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Re: What is Max Frequency of the commercial ASIC u hav desig

500MHz 0.18um

 

• Mar 3, 2005

• #15

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sanJerry2004

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40M CPLD in IEEE488 only

 

• Mar 4, 2005

• #16

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moorhuhn

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Re: What is Max Frequency of the commercial ASIC u hav desig

100MHz .13u,
150MHz .13u,

Are those who mentioned 500MHz and above still using classic synthesis, usual clock tree balancing and .lib based timing analysis ?

 

• Mar 9, 2005

• #17

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ryang

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Re: What is Max Frequency of the commercial ASIC u hav desig

sunms said:

2.5GHZ, serdes, 0.13 ST

Click to expand...

Imcredible

 

• Mar 9, 2005

• #18

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eternal_nan

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moorhuhn,

For the most part, yes, synthesized logic, cts, place and route, etc. All datapath components are done using mc, pipelines almost optimally balanced, etc. The floorplanning is done very carefully, clock tree synthesis is very closely controlled by hand (even though cts tools are used) and lots of manual timing fixes are applied. At these speeds power grid design also becomes an important issue.