What is Lock-up Latch?

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kumar_eee said:
Can anyone tell me about the lock-up latch?
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My experience with lock up latches is with DFT. If you have a scan chain with multiple clock domains in it the scan insertion tool should group registers from the same clock domain. Then a lockup latch is used when going between the two clock groups. I.E reg_group_clka -> latch -> reg_group_clkb. Usually the gate of the latch will be driven by clka inverted.

The lock up latch will insure that data is passed from register to register on every clock tick. It will prevent issues that can happen with async clocks that are skewed, I.E cruise through...
 

For DFT Compiler, lock up latch is inserted automatically if you turn on "-add_lockup true" for "set_scan_configuration".
 

Lock-up latches are used to allow scan chains to cross the clock domains.
They mitigate the skew between two clock domains to ensure data is shifted reliably on the scan chain.
 

If there is a neg edge FF before a pos edge FF, the data read may be the older one or the updated data is lost. This is probable in multiple clock domain designs
to make sure this doesn't happen, we use lock up latches.
 
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vivek_p said:
Lock-up latches are used to allow scan chains to cross the clock domains.
They mitigate the skew between two clock domains to ensure data is shifted reliably on the scan chain.
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Hi,

Is there any particular document which explains lockup Latches with timing diagram and all the possible scenarios where it can be used???
Thanks for the help.
 

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