what is linting and need tutorial for spyglass

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rocking_vlsi

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Please provide me tutorials about linting using spyglass. Do we use any scripting language in linting ? if yes then which one?
 

Lint Checks are RTL checks which checks for unwanted latches and RHS != LHS Basically make sure there are no surprise after synthesis.
Training material you can search GOOGLE
 

Linting is a RTL Verification tool that checks the quality of the RTL code and find out any violation wrt to certain policies dictated by a group of companies. It will raise for almost all sort of errors like inference of latch as mentioned in earlier post to presence of logic in the top level file of the RTL. It is the responsibility of the designer to go through each error and find out whether it is really an error or to waive it off.

Coming to your second Q: No seperate scripting is required other to run the tool. Alternatively GUI mode is also available.

Tutorials can be downloaded from net.
 

Is lint checking done on Verilog design or gate level description. How cross domain crossing error will be identified.

Please provide some links to download tutorials.
 

That CDC checks That is different compared to lint checks
 

Verilog Code is verified through Lint check. Now a days gate level description is also verified through lint sometimes but i am not sure whether the SPYGLASS tool has the capability to check it. In Lint we have a seperate flow called CDC methodology which will highlight all CDC based errors.
 
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