in the cmos there are intrinsic bipolar bjts. if you check the diagram of the cmos with n well you can see that the source and drain of the pmos is p+ and the well is n. and the substrate/body is ptype. so it can work as a pnp transistor. similarly there are other intrinsic bjt's. these are called parasitic transistors as they usually badly affect the working of the cmos. when the n mos also is combined there can be npnp thyristor structures. these can shoot up the Vdd and gnd lines when triggered. this is called latch up in cmos.
in the recent fabrication technology the latch up problem is solved to a great extend using the technology called as deep trench isolation
body effect: in the cmos we do all the connections, measurements etc with the assumption that the substrate or the body is at ground or zero potential. that is the ideal condition. but in the real scenario it is not the case. the body can have some potential there by changing the Vsb. changing vsb can affect the threshold voltage of the mos. so usually we connect the body terminal to the source teminal keeping vsb = 0;