What is IR drop? How to avoid .how it affects timing?

What is IR drop? How to avoid .how it affects timing? in which stage this problem will come and in which stage need close the issue.

IR drop, is close to EM, and this could be solve at floorplan phase with a good power structure, or with the metal filling after the routing/si phases.

1. The power supply in the chip is distributed uniformly through metal layers (Vdd and Vss) across the design (Power planning). These metal layers have finite amount of resistance. When voltage is applied to this metal wires current start flowing through the metal layers and some voltage is dropped due to that resistance of metal wires and current. This Drop is called as IR Drop.

For example, a design needs to operate at 2 volts and has a tolerance of 0.4 volts on either side, we need to ensure that the voltage across its power pin (Vdd) and ground pin (Vss) in that design does not fall short of 1.6 Volts.The acceptable IR drop in this context is 0.4 volts. That means the design in this context can allow upto 0.4 volts drop which does not effect the timing and functionality of design.


2. I hope you know the relation between voltage and delay tradeoff. If there is no sufficient amount of voltage, The delay will increase which affects timing. I hope u understand.

For more details on IR drop Analysis, Refer followed link http://www.vlsi-basics.com/2013/08/ir-drop-analysis.html

Thanks,
Alam