What is INL in D sigma ADC

[moda]

inl sum adc

Hello, what is INL (Internal non linearity) in D sigma ADC, I know in general what is INL but my Q is:

When i will go to full scale of the input signal of the ADC is it the worst case for the non linearity?

And what will happen if i will decrees the input signal? INL will be better? or not?

Thank you

Moda

 

[R00KIE]

adc inl definition

I do not know what is INL, you should write it the meaning the first time you give the acronym, but as you sayed the worst case is when you go full-scale because the switching frequency will be lower, so the IBN (In Band Noise) will be higher.
depending on the feedback gains and the input signal amplitude the modulator can even stop switching while the input signal does not decrease.
this is a "delicate" matter when it comes to calculate everything, or you use the full available voltage (at the output stage) and allow the IBN to be higher or you do not use it and the IBN will be lower

 

[mr_chip]

delta sigma integrator linearity issues

Usually INL means integral nonlinearity, not "internal",which is (as dscribed in Johns&Martin) the maximum deviation of ADC transfer characteristics after gain & offset errors have been removed. If I follow that definition, your question makes no sense..

Please explain again what you want.

Usually when talking about SD ADC (or modulator alone) performance, such metrics as DR (dynamic range), SN(D)R (signal-to-noise (plus distortion) ratio), SFDR (spurious-free dynamic range)

 

[Vamsi Mocherla]

inl adc performence

Firstly, INL is the integral non-linearity for any ADC. When there is a discrepancy in the response of the digital code from the ideal one is called DNL(differential non-linearty). When you sum all those differences(or integrate them mathematically), you get INL. It is a measure of how good your ADC is.

Hey measuring INL for sigma delta ADC is not really that critical because you will be only working mostly on a single level modulation. The beauty in ΣΔ, is that you will get all your resolution in the digital domain after the decimation process. Even in extreme cases, I do not think that people use more than 3 level comparision. Hence INL and DNL are not really that critical for Sigma delta

Hope it helps.............

 

[xwcwc1234]

inl adc measurement

If INL and DNL are not really that critical for Sigma delta, how to characterize the performence of delta-sigma ADC ? SNR or SNDR are usually used for delta-sigma ADC performance measurement , is that enough ?

 

[Vamsi Mocherla]

adc worst case analysis

SNDR and SFDR are the most important measurements in Sigma delta. One more thing is how your noise is shaping. More than a measurement it is an observation.
Other critical things are the gain of the integrators(in case of multiple order) and the Leage through them.

 

[moda]

what is inl

Thank you all for your effort and your comments.

But In my case INL is VERY important!!!

I have found that if you will reduce the input signal the INL gets better.
If you are interested look for example at the ads1271 figure 30 on page 12

I will be happy to get your comments.

Regards

Moda

 

[Vamsi Mocherla]

Dear moda,

Definately the INL increases over the increased input range. INL is the total sum of deviations(DNL) over the full scale range. In the case of sigma delta, as you increase the input range(Voltage), there will be a problem in linearity. This is because for a mutliple order(which could be the case in order to achieve higher bits), there is a problem with the second stage(integrator) getting saturated. Hence some non-linearity will arise. In my experience, if we had a VDD of 2.5 V, we never exceeded the input swing by more than 1 V in order to avoid it.

Also, as per your reference, in ads1271, the INL deviation is about 6ppm which is about 0.3 LSB. I do not think that the INL figures like these will really effect your performance.

I hope that I am clear............

 

[moda]

Hello Vamsi
Thank you.
About the 0.3lsb, I do need high stability, this is for new project, high linearity, stable with time and temperature ADC, in the 0.3LSB range its ok as long as it remain LESS then that and not more, at all input voltage range.

So to see if I understand what you mean, is that non linearity depends on the integrator?

Regards

Moda