what is difference between layout exchange formate and library exchange format?

[skn.1357]

Hello there
what is difference between layout exchange formate and library exchange format? are they both represent the same thing or are different??
thanks in advance...

 

[yadavvlsi]

Library Exchange Format (LEF) is a specification for representing the physical layout of an integrated circuit in an ASCII format. It includes design rules and abstract information about the cells. LEF is cadence propitiatory. Design Exchange Format (DEF) represents the complete physical layout of an integrated circuit while it is being designed. DEF is used to exchange layout across various physical design tools or with in same tool. So you can call a DEF as layout exchange format.

 

[jeevan.life]

Library Exchange Format (LEF) is a specification for representing the physical layout of an integrated circuit in an ASCII format. It includes design rules and abstract information about the cells. LEF is cadence propitiatory. Design Exchange Format (DEF) represents the complete physical layout of an integrated circuit while it is being designed. DEF is used to exchange layout across various physical design tools or with in same tool. So you can call a DEF as layout exchange format.

LEF is more metal specific where as DEF is placement specific. DEF defines the absolute location of the cells as well where as LEF does it only for the layers used. ".lib" is the library or reference book for the pnr tool to extract timing and logic info required for the cells used in the design.

 

[skn.1357]

LEF is more metal specific where as DEF is placement specific. DEF defines the absolute location of the cells as well where as LEF does it only for the layers used. ".lib" is the library or reference book for the pnr tool to extract timing and logic info required for the cells used in the design.

Thank you very much for reply...

 

[rca]

Def could contains netlist, routing, placement, scan info, port...
Lef is a simplify view of macro/pad views instead using GDS, that should contain the pin (metal position size type) and obstruction to allow the PnR to route it.