Sep 5, 2007 #1 Q quan228228 Full Member level 4 Joined Mar 23, 2006 Messages 196 Helped 16 Reputation 32 Reaction score 3 Trophy points 1,298 Activity points 2,571 +delay_mode_unit what is "delay_mode_unit" for ncverilog tool? Could you give me an example? thanks! David
+delay_mode_unit what is "delay_mode_unit" for ncverilog tool? Could you give me an example? thanks! David
Sep 5, 2007 #2 avimit Banned Joined Nov 16, 2005 Messages 412 Helped 91 Reputation 182 Reaction score 23 Trophy points 1,298 Location Fleet, UK Activity points 0 nc verilog timescale When applied, all the delays anywhere in your design, such as cell delays in netlist are set to unity. It is used while running nelist sims, to just make them faster. Kr, Avi http://www.vlsiip.com
nc verilog timescale When applied, all the delays anywhere in your design, such as cell delays in netlist are set to unity. It is used while running nelist sims, to just make them faster. Kr, Avi http://www.vlsiip.com
Sep 5, 2007 #3 Q quan228228 Full Member level 4 Joined Mar 23, 2006 Messages 196 Helped 16 Reputation 32 Reaction score 3 Trophy points 1,298 Activity points 2,571 delay_mode_unit avimit said: When applied, all the delays anywhere in your design, such as cell delays in netlist are set to unity. Avi http://www.vlsiip.com Click to expand... Where, what does "unity" mean? David
delay_mode_unit avimit said: When applied, all the delays anywhere in your design, such as cell delays in netlist are set to unity. Avi http://www.vlsiip.com Click to expand... Where, what does "unity" mean? David
Sep 5, 2007 #4 avimit Banned Joined Nov 16, 2005 Messages 412 Helped 91 Reputation 182 Reaction score 23 Trophy points 1,298 Location Fleet, UK Activity points 0 delay_mode_unit ncverilog unity means 1. So all your delays throught the design are set to 1 ps or ns or whatever your timescale is
delay_mode_unit ncverilog unity means 1. So all your delays throught the design are set to 1 ps or ns or whatever your timescale is
Sep 5, 2007 #5 Q quan228228 Full Member level 4 Joined Mar 23, 2006 Messages 196 Helped 16 Reputation 32 Reaction score 3 Trophy points 1,298 Activity points 2,571 ncverilog no delay avimit said: unity means 1. So all your delays throught the design are set to 1 ps or ns or whatever your timescale is Click to expand... for example; timescale 1ns/1ps assign #3 a = b&c; after adding option "delay_mode_unit", the NC-VERILOG tool assume that the delay value is 1 ns, not 3 ns. right? David
ncverilog no delay avimit said: unity means 1. So all your delays throught the design are set to 1 ps or ns or whatever your timescale is Click to expand... for example; timescale 1ns/1ps assign #3 a = b&c; after adding option "delay_mode_unit", the NC-VERILOG tool assume that the delay value is 1 ns, not 3 ns. right? David
Sep 6, 2007 #6 B beta0 Member level 5 Joined Nov 24, 2003 Messages 88 Helped 7 Reputation 14 Reaction score 2 Trophy points 1,288 Activity points 393 ncsim assign # delay mode quan228228 said: avimit said: unity means 1. So all your delays throught the design are set to 1 ps or ns or whatever your timescale is Click to expand... for example; timescale 1ns/1ps assign #3 a = b&c; after adding option "delay_mode_unit", the NC-VERILOG tool assume that the delay value is 1 ns, not 3 ns. right? David Click to expand... no, delay mode is used for cell delay
ncsim assign # delay mode quan228228 said: avimit said: unity means 1. So all your delays throught the design are set to 1 ps or ns or whatever your timescale is Click to expand... for example; timescale 1ns/1ps assign #3 a = b&c; after adding option "delay_mode_unit", the NC-VERILOG tool assume that the delay value is 1 ns, not 3 ns. right? David Click to expand... no, delay mode is used for cell delay