What is Contamination delay in digital circuits?

[vlsi_whiz]

contamination delay

All of are familiar with Propogation delay in digital circuits. But what is contamination delay and how does it occur? Any insights?

Does contamination delay also play a part in the total delay of the circuit?

 

[tarkyss]

what is contamination

the contamination delay is the minimum amount of time starting from when the input to a logic gate becomes stable and valid to the time that the output of that logic gate begins to change. The sum of contamination delay and the amount of time it takes for the output of the logic gate to become stable and valid is the propagation delay
When designing circuits, it is often desirable to increase the contamination delay to approach the propagation delay as much as possible, while not increasing the latter (for example by ensuring that all possible paths are equal length). Doing so ensures that the previous valid data is stable in the output for a longer time, while not delaying the propagation of the new valid data even more.