what is C@dence firstencounter2.1 for linux?

[gqxfw]

who can introduce cadence firstcounter2.1 for linux?
thanks

 

[DeepIC]

a floorplan tool

 

[net_light]

FE is not just a floorplan tools

hi, everyone:

FE is not just a floorplan tools. Actually it does a lot:
1) final legal placement with logic group constraints
2) trail route, it's a detail route, just skip the search & repair
3) final power struct. design and power route.
4) IPO
5) CTS
6) fast 2.5D RC extraction (1M gatecountes runs at several seconds)
7) IR drop analysis
8) integrated DC & STA
9) support hier. design:
a) partition
b) block-pin optimize based on trail route
c) hier. clock tree synthesis

and the most important is it runs so fast! for my 5M design, I can run 2~3 iterations in one day! the best tools I have seen.

 

[seasonyangd]

I dont think fe can do so many things. Cadence have a set of tools called SOC which include firstencounter, RTE, Simplex etc. It support all of the work of VDSM backend design.

 

[net_light]

yes, I know, CDN new product SOC-Encounter is FE+SEPKS+CELTIC+NANOROUTE. But FE can really do what I said.
PKS is used for difficult timing closure block. CELTIC is a crosstalk analysis tool but integrated into PKS and FE interface now. Nanoroute now native integrated into SOC-E in 2002.3 release. which mean the final detail route now need not dump out LEF DEF and invoke nanoroute and import the LEF DEF to finish routing and dump out again and read back to FE. Now the nanoroute engine is a part of SOC-E. very cool!

 

[cdic]

That is true, but how about the performance? I don't think it's good enough to handle everything.

 

[net_light]

I ever tried a 2M gate counts design, std-cells as 500K gates.
more than 120 ram modules. FE place only 45min and trail route spent
about 20min. RC extraction spent just several seconds. can you found any other tools that can run so fast?! this is really called high performance!! and please remember the placement has the tape-out quality. I love this tool.

 

[johnnyh]

According to Samsung semiconductor internal try run, Cadence FE is the best performance tool to handle more than 10M gate count, compare with Synopsys PC.

 

[armer]

SE

Does SE54 has linux version.

First Encounter FE100
------------------------------
SOC22 FE100 CD
SPR50 80000
------------------------------

SOC Encounter
------------------------------
SOC22 FE200 CD
SPR50 80000
DSM54
RTE11
------------------------------

 

[cdic]

I ever tried a 2M gate counts design, std-cells as 500K gates.
more than 120 ram modules. FE place only 45min and trail route spent
about 20min. RC extraction spent just several seconds. can you found any other tools that can run so fast?! this is really called high performance!! and please remember the placement has the tape-out quality. I love this tool.

--- Don't tell me it's e@gle design. As to my experience, it's not very good for timing-critical design, maybe fit for very large design only.

 

[Nobody]

When i install SOC . It ask me to refer the work order file . It's a file encrypted some ascii text. Does anyone have the solution to by-pass this step to install SOC.