What is Black Box in Netlist and How to Define It and Identify It?

[ReubenMijares]

1.) What is a black box in a netlist?
2.) Why do we have it? Is it to hide the IP?
3.) If you are looking in a netlist, how can you identify that a module is a black box?
4.) If it is a black box, does its module definition needs to be present to compile the netlist?
5.) If you are going to synthesize, how do you specify that a module should be treated as a black box?

 

[anilineda]

normally synthesis tools wont synthesize memories, if your design contains a memory block then you should keep srams blocks in the place of it. If those sram macro blocks are not available the you will black box or commented out in your RTL and perform synthesis. now the synthesis tool will consider this commented out memory block as a black box.
2. it is not to hide , for IP protection many follows rtl encryption.
3. in gui pane, that particular block is get locked or you can see in synthesis log file , if u double click a black box, it wont open further.
4.for GLS, gate level netlist simulation , every module definations needs to present .

 

[ReubenMijares]

normally synthesis tools wont synthesize memories, if your design contains a memory block then you should keep srams blocks in the place of it. If those sram macro blocks are not available the you will black box or commented out in your RTL and perform synthesis. now the synthesis tool will consider this commented out memory block as a black box.
2. it is not to hide , for IP protection many follows rtl encryption.
3. in gui pane, that particular block is get locked or you can see in synthesis log file , if u double click a black box, it wont open further.
4.for GLS, gate level netlist simulation , every module definations needs to present .

So that means a blackbox is an instantiation of a module whose definition is not in GLS model but in RTL or behavioral?

 

[dpaul]

So that means a blackbox is an instantiation of a module whose definition is not in GLS model but in RTL or behavioral?

Not always true.
A black-box can also be an RTL module with no logic defined inside. Like you have a Verilog/VHDL module with just the top level ports, the input ports are not connected to anything and the output ports are driven to their default values.....this can also be considered as a black-box.