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What is be the core and I/O voltage supply in 65nm technology?

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suhas_shiv

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I wanted to know what would be the core and I/O voltage supply in 65nm technology. This is for the design of a LVDS transceiver. If anyone here has the values for it, could you please share.

Thanks,

Suhas
 

Re: 65nm Technology

HI,

Standard IOs, in which the substrate plugs are connected to the same node as the NMOS source and the Nwell ties are connected to the IOs positive supply.

Isolated/split-vdd (ISV) IOs, which are totally separated from the substrate by Niso layer and surrounding nwell rings. The Nwell ties are connected to a dedicated positive supply. This strategy avoids propagating noise from the IOs to the substrate.

SALAM
 

65nm Technology

TSMC offer core 1.5, I/O 2.5, 3.3
 

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