what is "Assertion-based" verification?

System Verilog & OVA claims to be Assertion based verification.

I don;t understand what is so called "assertion"

What is the difference between the Assertion based and the Verilog based verification?

If we are using verilog as testbench, is that considered assertion based? if not, than what method ( or what -based?) is that?

Hi,

Assertion is widely used in software engineer.
Assertion means the logic *must output* that way, if not, the logic must be wrong.
Check the assert function in <assert.h> in C language.

For example,
//--code--
assert(x>0);
//--code--

If x<0, the program will show you assertion failed.

Like in software, hardware can do assertions like that, but the procedure is more complicated!

For example,
@(posedge clk)
if logic_output != 0, assertion failed!

I think you may refer to OVL(open verification library), search it in Google.

The difference with testbench and assertion is:
testbench is stimulus and monitor but assertion is to add some testpin in the logic.

BTW, I will study OVL in few days, and if you are interested in it, we may have a discusstion

Regards,
Davy

hi,
simple way to describe this is as follows -
in digital verification you only probe some singnals at particular times which means that you go unaware about what happens to other signals at other times -assertion means 'to assert' - it is a way of writing expressions on a signal or group of signals to continously monitor these signals throughout the simulation - that way these signals are no longer on your blind spot - it is possible to add warning and error messages when an illegal state is encounterd and even to stop simulation -
an example is if you have two signals A and B and you want that they should be mutually exclusive at all times - you can write a assertion for this and then you don't need to stimulate or probe these signals - they will automatically be monitored based on their connections to other signals -
hope this helped -

ag

Hi all,

Assertion are usually writed in the input interface.
It can point out the bug where it take effect first time. The concept is that if the input is garbage, the output is garbage. We can know that the error is from the precedent module. In the tradition simulation/debuging, we can only check the finally ouptut is right or wrong. If it is wrong, we must trace back to locate bug.

The link that is taking about assertion before


Sincerely,
Jarod

With an assertion based methodology, you specify a set of rules that must be proved statically. A mathematical model is then produced form your source code and confronted to the rules set. If every thing is OK, then the design is validated. Otherwise, you get counter-examples.

there are some kinds of assertions:
must be; must not be; performance ...